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DATE: 02-13-2015 HOTFIX VERSION: 043" N8 I( ?2 t. g2 L3 e0 K
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: a8 Q! y) `- h. J5 J8 O2 H1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW
4 c& K+ n. w- k6 j0 `5 W$ T1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected* l$ e9 B' a* X$ V8 y( a7 T9 q: i
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.6 @' |' n$ e9 w$ o
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
, I8 R4 }( F( T* n7 ~( ~, J1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
. F h. A2 k- X9 V: n. t1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
' @' J# i+ A: ~! J" [1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs" [( h. n1 W* I; q4 B' C1 ?! ^
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols
% i, y; } K( G6 B2 d# l1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
" @3 P }9 C$ R* \: P1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
! n5 Y* ?( b [# ?! }1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM* f: `2 V; I8 B4 L
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors* P6 p" g- h% b3 t, M" G
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete& v b* f! p" I6 S3 D' b( J
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes& E% T' B+ o- H N% d
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design# k- B4 P2 n* M' ]
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
8 r6 X6 i# o M8 G+ H1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
9 N3 K7 t3 x* Z7 T/ Q1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
8 W) Y' n1 l3 m) ^1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape( X3 p) W: w5 U$ T" D+ _& p0 L
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DATE: 01-30-2015 HOTFIX VERSION: 042$ P: D3 { w% E# |* }8 `8 `
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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+ _9 ]0 K4 k4 X3 S1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
& v1 R/ @: l1 _. z; J+ a- N* J* O1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
3 m( Q- E: J; y5 s. c: v( l1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
* t( A& ?3 A8 R; x1349849 CIS OTHER Capture crashes on generating variant reports8 Z2 T' a: D {& r" ^" ?
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
& {$ s- L4 w8 @1 M1350477 PSPICE SIMULATOR RPC server is unavailable1 ^0 @9 A; F' y4 h1 y& N1 |7 q! W
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash, i# Y' C& {" ] ?9 ]4 d8 y
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property4 f! I* h. h! b+ V
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
/ m( p9 U) m6 |3 L; A1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers" O! o4 I. N: K
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase! g z8 m& {' E+ i7 z$ u5 [* q, u
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
" n4 C( K" S Z, @6 s1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
& @* q9 O% F2 X( I9 O% R1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
0 G- X' O. j0 N: M$ t1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
" Q0 V: q+ B3 b0 s4 P1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.; _8 f) Q( W& |
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design1 {" p9 o' G- M2 g# [" a1 \
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor" }# N0 ]2 q$ h# d* ~
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.. H9 e8 p+ G9 e' O, Z& h
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.& w) x) j8 E: S
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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