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DATE: 02-13-2015 HOTFIX VERSION: 0434 b5 S4 H1 E& G8 R; m. @
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3 J7 r& M: s+ q& e* ]& w% fCCRID PRODUCT PRODUCTLEVEL2 TITLE
& y; _; t. o$ p% p* Y===================================================================================================================================, }, m7 V5 Y8 Z1 M
1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW
) v/ z2 L% T' b( I4 d; L1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected. v/ @# K4 D. G; O( A
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.. x9 t) } Z5 P/ w! R
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
$ _3 A& |, W/ J3 e1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error6 q5 q, X! C4 u) s. a$ I4 e) I
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
* Y) [+ Y, R" b9 P" |6 m3 d1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs. Z. p- Q- H5 k( g3 G6 y* E
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols, e$ c# D1 L' ?* a
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
# W4 h# G! q8 r3 c1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
: | W: ? U+ p% Y, Z! g2 `1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM, v: m1 _- x# M9 s
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors8 }$ u( ^$ I4 x5 w" |3 K w
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete) \6 g3 m' A$ Y+ k3 `/ [
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
) d( N, w: [, J3 e' L0 Q* D0 r1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
9 A7 ]- a u) M9 A( H" X1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
4 R! K H( K5 C8 t2 ~4 g1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
; D; |. z5 \7 e1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file. y; \( Y$ _4 x# y1 [! c) Y
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape5 a0 Z% r* [$ z/ y
- X1 T/ d" C; G4 [, I: C0 E/ UDATE: 01-30-2015 HOTFIX VERSION: 0425 f8 K. p* j1 l# y9 g0 {8 P4 Y
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6 O/ W8 w' E! m( l7 l7 d3 gCCRID PRODUCT PRODUCTLEVEL2 TITLE0 H% \5 F g+ A8 D. b* |
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1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines- c% t( X& L y4 M, v( s
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
0 Z4 X2 L9 ^# j4 m3 a1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.- ?) w4 q; s# O, v r
1349849 CIS OTHER Capture crashes on generating variant reports. g5 M* ~& W( t# x4 G- o; k! s, n' ?
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec0 W, Q, E/ j5 g
1350477 PSPICE SIMULATOR RPC server is unavailable
! P/ u. f: k9 M5 V1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
1 t; L9 f1 ?6 Y8 M% o; m1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property/ t. x5 ~6 |6 n! j2 f; k
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
I ?) x; @7 n) ]4 a7 K1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers& w+ _6 O, L2 _/ D3 u6 c4 D
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase' [# c2 j0 V8 Z, E1 N4 v
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
) M, \, T; o* P+ j1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to+ I. ?! ^: r2 w5 R
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
s. [7 K, q$ W1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.8 F, v1 u- |& D& R
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.4 L. f9 Y; d6 f2 X# ^( z2 r
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
. C1 V l# W& v; M9 g2 P: Z1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
6 \ [4 u8 B, {: i, [ K. R1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
- T5 F* w5 p7 b# F) k! Z1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
1 n3 b+ i/ }# {3 A& B1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.0 Q0 _& L" ?' O" Q0 G, `9 }
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发表于 2015-2-15 23:37
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