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g! V! d0 ]; r1 FDATE: 08-22-2014 HOTFIX VERSION: 0344 ]) h8 U: [ k# t" _5 i' o4 H" {
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CCRID PRODUCT PRODUCTLEVEL2 TITLE, g7 u+ i( W: L% Z: W+ L! B
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3 j$ f: j5 o5 j. z( I+ X8 p0 k$ O4 g6 B932528 CONCEPT_HDL OTHER Ability to handle reusemodule in soft reuse blocks.
- B( T0 b" c; O" H# Q1137838 FSP GUI Ability to add notes to the canvas2 F, T# k& _& Q# K: G& @* D( R3 `* e
1274382 ALLEGRO_EDITOR OTHER Retaining rats at the end of the clines or vias1 { b; [4 H0 y( l5 @
1283575 FSP DE-HDL_SCHEMATIC Force Schegen to use symbols from released library
! l0 \0 p6 U$ A' J+ g0 s6 \7 S$ D" C1296331 CONCEPT_HDL COMP_BROWSER CSV export no longer works properly from Component Browser6 K' t* T# s/ i" d" h
1297855 F2B DESIGNSYNC ds -automode error
* ?& s: b3 z/ ~5 `7 |1298028 CONCEPT_HDL CREFER CreferHDL crashes7 D: r3 j" g1 ]( u% m. Z
1299607 SIG_INTEGRITY OTHER AutoModel should generate ESpice models for illegal values
5 Z2 q; w3 o. M2 P/ P+ m1299609 CONCEPT_HDL OTHER AutoModel should make an ESpice model for a 3 pin Capacitor
+ V/ ?7 a& V, q4 n( |* `3 c1302013 ALLEGRO_EDITOR EDIT_ETCH AiBT Crashes Allegro for nets having T points
: q# b/ E4 x/ k1302209 SPIF OTHER Can't Export to Router and create a Specctra file.
; `8 w* b( ~& D. X6 [1302242 F2B PACKAGERXL Packaging a hierarchical project does not create a full pstdmodeldat file
& L0 U/ A- O# a) f4 B# g1302285 SCM CONN_SERVER DSCS-120: Failed to open file <filename.xcon> in write mode; e3 D0 a+ X0 a3 p0 Q* j5 {
1302310 ALLEGRO_EDITOR INTERFACES Need way to have user defined license packages win over Cadence products.6 N- {7 m4 s$ J
1302638 F2B PACKAGERXL Function swaps are not backannotated into the schematic
: w# [# G9 a8 X$ O2 L1303170 SIP_LAYOUT DIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part
6 ^& V+ P0 D* l# K8 r1303214 CONCEPT_HDL CORE DEHDL crashes& ~- k' ]* f8 q
1303219 ALLEGRO_EDITOR COLOR The user preference variable color_dlg_auto_apply changes the colors in the Display category1 J, p h8 v* z) D }$ ]
1303685 CONCEPT_HDL CORE DEHDL crashes when I save page 39 m1 ?: C% F, _2 J
1303897 CONCEPT_HDL CORE Tool crashes intermittently when editing top-level schematic+ R* j6 L" q3 \- V
1304656 APD PLATING_BAR Add Plating Bar command convert the Clines having Arcs to 45 Degree segments
2 E/ |# l; N0 ^. Y' w1306467 CONCEPT_HDL CORE Concepthdl crashes during model assignmnt
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功能上的更新了 color_dlg_auto_apply 应用；勾选了此项后；设置颜色时不需要点击应用按钮了；显示很直观哦! {( Z; H7 ~7 K. v3 J
大家来试试吧
B$ b9 K: e, D* D2 C不足之处就是出钻孔文件导入cam350时单位精度还是有问题的；特别是勾选了CAM350后比例更加有问题。- q4 k# P: E/ G. {
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发表于 2014-8-25 20:15
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