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DATE: 02-13-2015 HOTFIX VERSION: 043! I1 P% L( ~% f, K) ~
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0 x4 w: o) y6 ^( T8 j% g9 F% jCCRID PRODUCT PRODUCTLEVEL2 TITLE
0 t# @, q1 U. S. m4 F& _% E, i===================================================================================================================================
" n4 D- F, z7 R/ w- j* i) d, S2 U& ]1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW! `% n8 j% t( P2 U
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected7 K2 ^8 I9 r* s2 Z. b \
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.) R$ c. f `1 @( v2 Y
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
' L) \1 e+ V& [" R7 d: e, g1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
0 o* A1 D6 `" u$ u1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference& f0 U$ c2 W" l
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
( `: n& ]# ]4 u0 H5 z1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols* {& ~) J- B8 g, r5 k. d
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent9 m+ K6 ?( P2 W5 f4 P- @+ B
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
7 P s5 h6 V" Q; \% R& c1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM6 Y ^, M) \. R) O) d9 c& |
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors" F4 B* E: w+ n1 a5 @ P
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete1 k# t, x% O- m
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
3 h+ g. A( o9 ?5 ^. o1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
# I' g! R* T0 Z/ A1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
$ ~3 a* k+ J, V; t: e1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
& Y$ {+ w. m' |5 c5 ]# q* J1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file2 c8 g! ]+ ~; |8 a2 U
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape
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5 j A% K' l% S {DATE: 01-30-2015 HOTFIX VERSION: 042+ o8 A$ v* q- t7 l
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ O5 s$ N7 G) `" q4 `! H===================================================================================================================================
# ?3 `; \ ?/ U/ p# `1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
' S1 ] b R. ~! x6 x- m6 {1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
1 k: ~6 ? x! X/ B2 E* R" H9 x1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
. _5 J5 E$ v8 _. q1 @1349849 CIS OTHER Capture crashes on generating variant reports
: Z" s% J$ |: x. ? F- \: `$ X1 d1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
+ Q0 J6 U4 [, B8 t. t7 q" C+ Z1350477 PSPICE SIMULATOR RPC server is unavailable6 W4 B! X. l9 D; k X8 n
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
3 n/ o+ o" t P9 `- n4 Y j1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
( E# E& F; {2 l1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
: p. F1 p+ ~: D* k1 U8 T1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
% M* x2 s6 N0 A$ J1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
3 X9 D8 q/ d7 y$ T1 M% X1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.1 C- @* D3 a- v- J1 d
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
9 w) Y9 ^5 v% ~1 M/ k7 x2 T1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
4 @0 k* \) D( w) t1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts." A! G" F- b! m y, N% H
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
& Q, { R8 A1 F4 H, Q/ j1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
! b$ [( d: [2 i1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
0 P, W" T& C5 p3 c' D1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.8 p$ z! N/ M" n2 j# }
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
0 P( @( ]4 K% D1 D9 x) O1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.+ P* c% D; D9 D5 I& n
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发表于 2015-2-15 23:37
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