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DATE: 02-13-2015 HOTFIX VERSION: 043
3 @2 `; V4 M# r" N* i- {& K0 d===================================================================================================================================6 O3 b- A3 j2 {
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ ^3 g7 _9 e* T- z" [
===================================================================================================================================5 }2 q1 o ]( d* p' k( ^' B
1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW
6 p# `( G" c4 q9 L; f- U9 q1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected# {7 j0 N8 |+ g0 c9 E+ {6 \% k
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.2 M, N/ B4 Z( P( B
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window! E8 j4 p& W# D) E# l# v
1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error4 l7 ?' Z8 T, ]
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
T% g9 [ o* m9 x1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
# I! k9 M4 v0 i* o# q0 A) \1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols# q$ D8 ]' k2 v; Y0 [
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent a4 x* c) @1 O+ ^9 w) f
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
# T% t, p5 H# L% Q+ t5 l1 Z1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM1 y& x, C6 n1 B( M
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors' `! |8 P- B2 V; r6 p9 r% f
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
) h; h0 u' `' o& k& k9 H' E1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes' e ?( [* Y" q! I0 u) p
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
/ o+ S; J5 R) ]" }, a" w( K- N G1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers. d0 O1 j) ^4 y' d( _
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design, x% H0 X! _' h
1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file; u+ ?' C6 n7 V( c p- d- K- A$ |
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape
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DATE: 01-30-2015 HOTFIX VERSION: 042, b! a }; E& m5 N0 g& \: |) c4 I
===================================================================================================================================" d8 _0 x: w4 Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 W) Z" N0 r- z0 w* O) e===================================================================================================================================0 w% U& P1 d5 V* I b: L4 h' S
1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines4 u1 Q% V% e' J, {9 j c# _# _
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
+ w( a! o$ {! P0 l2 }" ?1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
3 j0 k1 k+ `. B: w1 s1349849 CIS OTHER Capture crashes on generating variant reports
' X7 y1 `- B+ _8 z1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec3 v2 k0 j/ o' J6 [5 v* _- ^
1350477 PSPICE SIMULATOR RPC server is unavailable N. u! }% X" Z) b/ h5 N
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash! B6 `- b' Z0 H. N8 |7 r3 D: L
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property0 O" f% Y# @" M ?& d
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error./ r e9 \9 `3 P7 u6 d/ C& Y$ m9 m
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers- m6 }3 i2 N& L0 a0 U# u
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
4 v8 t% U5 Z' |" Q2 S1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.: z' V' d; p2 R
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to* t1 s8 T& j! ^. B
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly% P( A" T, q3 ~# T% y) z
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.! {- @2 h- W' p. ?; L, M
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.8 g! [" o& z9 Q l* V# |
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design
+ V) A1 F2 E0 L1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor- {2 d1 f/ |# J
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.: D+ ~, _+ X1 e- L, C
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
( c. }7 O) ~# b) i F1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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