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本帖最后由 zgyzgy 于 2015-9-13 21:16 编辑 # F+ L2 T* o; m
. U6 O7 |* i- g5 c: q" UDATE: 09-4-2015 HOTFIX VERSION: 057% |: [" X3 F$ O7 f3 }+ g
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 v* _+ Y; t. q/ {* P) G4 j===================================================================================================================================, F# g! I+ N' `7 d
1249604 PCB_LIBRARIAN LIBUTIL Libexp verify runs both con2con and hlibftb
: C' ^+ ?$ ]* |% [1417327 CONCEPT_HDL PDF Omit mechanical page while printing PDF
& ^# O. r# T' n |$ S: d4 v- x1440484 CONSTRAINT_MGR CONCEPT_HDL existing pcb diff pair name is changed by netrev
6 u/ T3 S0 r# N9 Q* R1441086 PCB_LIBRARIAN OTHER Cannot delete pin & added pins change after save
' O1 f4 ~6 k5 g; \: l. w1448066 SIP_LAYOUT TECHFILE Using a script to export technology file from Constraint Manager crashes SIP_LAYOUT
$ b' l' G: d3 e' G1452431 CONCEPT_HDL CORE Obsolete $PNN is remained in a dcf file and Attributes dialog$ w! i# O2 b f3 o0 R) x- V
1452640 ALLEGRO_EDITOR OTHER Updating PCB Board file concern
+ o; C9 j6 u/ |! {+ m7 @# l1454730 CONCEPT_HDL CORE Zoom/Pan Disrupts move and copy
X2 q: w+ s( d0 k. B8 R1457713 ASI_SI GUI Setting Sigrity_EDA_DIR for Sigrity 2015 /OrCAD ERC
7 f- h# @* o$ o" p) g1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties
/ r$ S. J8 @1 ]& m1458461 F2B PACKAGERXL The pstprop.date file "Conflicts on Net Synonyms" are NOT reported as errors
/ l; l1 O! A P3 z0 Q1459153 SIP_LAYOUT OTHER Mirrored components with pads on diestack layers (above top/below bottom) display on right layer but aren't selectable., c d( \9 o' T2 B
1461553 CONCEPT_HDL EDIF300 edif300ui writer crashes on ADW design
6 q& G! A+ c* z ?' m: W5 }1462254 ASI_SI SPDIF Ball properties are not translated to XtractIM using SPDIF0 v; h$ Q: ~$ [+ }% r* @- F# K
1462441 CONCEPT_HDL OTHER Pin text alignment and overlap with symbol boundary issues on symbol rotate' s: S7 X3 z- Q+ z" G4 j, D
1463333 ALLEGRO_EDITOR INTERFACES PDF created using Export > PDF shold not zoom to Page fit when selecting another layer
/ i5 X7 V y$ ?1463358 ALLEGRO_EDITOR INTERFACES Color assigned to pin not passed to PDF
3 P+ N5 |) f; t% M& ?6 ~3 V1463648 CONCEPT_HDL CORE Need ability to block the uprev of a design
! o; ^: ^, {6 |1463839 APD OTHER Changing DIE property to another layer does not change its masking layer1 {0 P+ b& Y' U' }8 d
1464380 APD OTHER Why pad at wrong layer when we place SIP 16.6 but 16.5 is correct.+ l9 J5 z0 D3 d0 d! n
1464660 CONCEPT_HDL CORE Problems with "save hiarachy": r7 ?6 u+ B2 U5 }6 N' ?) h3 @
1464771 SIG_INTEGRITY OTHER PCB SI crashes when extracting differential pair topology from Constraint Manager
8 Q% Q0 V. c' M- [9 O- \8 m1464909 APD WIREBOND Bondfinger drifting off of the WB guideline# B/ i$ L( b3 m' @- P- e6 w7 N/ {
1465273 SIP_LAYOUT STREAM_IF Streamout with mirror makes die symbols not located at where they should be in gds. Y2 z2 Z1 h2 M: T) R- N1 Q) `( [+ p
1465457 CONSTRAINT_MGR CONCEPT_HDL Layer characteristics from a lower-level block are merged with the higher-level
- W& e4 k& I0 n1465541 CONCEPT_HDL CORE CM_VALIDATION_ON_SAVE is crashing DEHDL on startup
& X0 s# x9 f- [. G: K) ?1465543 F2B PACKAGERXL USE_PACKAGED_NAMES is crashing Export Physical
: z' M5 t% z }6 A1465911 CONCEPT_HDL OTHER Question about checks made in HDL while creating BOM" Q8 ` M' ]) t2 X# a( X) y
1465916 F2B DESIGNVARI Issues with variant management in ISR 055 #1 - Must save variant in Variant Editor to add info to CPM: o* Z( Z0 D1 O3 L4 z& Q
1466230 CONSTRAINT_MGR UI_FORMS The Clear option is missing from the Reference Electrical CSet field in all workbooks
4 g8 Y4 H/ E, j- C4 u1466404 CONSTRAINT_MGR ECS_APPLY ECSet mapping using tags not working. J' n! }4 k) {! o7 o
1466492 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Add Connect command6 x: Z! ~4 \& v8 J+ D/ G: Q; Y
1467156 F2B DESIGNVARI Out of sync endless loop
8 `2 E3 i/ M8 b, ~1469062 ALLEGRO_EDITOR EDIT_ETCH Crash while performing neck mode for Diffpair
- Z" @* y. ^. E. v {) W1469081 ALLEGRO_EDITOR ARTWORK Short in Gerber Data due to wrong cut out around via! o! m7 x3 K6 L. D; N$ F7 D/ Q( L: @8 w
1469713 TDA CORE Updating project with non-existing variant crashes TDO& N* N' i% x. K
6 T# A- E q* k8 x8 @" j正在上传文件中，分享链接稍后。。。。。。
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0 U8 U1 Z. |; i* ]$ w& ]http://pan.baidu.com/s/1qW3jhoC) ]% Z w% g0 e3 a
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发表于 2015-9-13 16:53
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