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本帖最后由 zgyzgy 于 2015-9-13 21:16 编辑 : @0 {6 q. \/ @9 F
: R0 m, n: T$ a: {6 S' MDATE: 09-4-2015 HOTFIX VERSION: 057
& B9 O3 ~$ J- Z& z! b# ?===================================================================================================================================
- M0 r* o) Y+ L& kCCRID PRODUCT PRODUCTLEVEL2 TITLE$ J/ R, @7 k d/ l- h8 a
===================================================================================================================================" y* l: j. B# D% I
1249604 PCB_LIBRARIAN LIBUTIL Libexp verify runs both con2con and hlibftb5 N7 E1 w1 j" ~% I7 }; l, T5 N. @
1417327 CONCEPT_HDL PDF Omit mechanical page while printing PDF1 D4 r/ u- `& E6 r- H
1440484 CONSTRAINT_MGR CONCEPT_HDL existing pcb diff pair name is changed by netrev; E" [5 S7 [% I& k, H" l
1441086 PCB_LIBRARIAN OTHER Cannot delete pin & added pins change after save& h4 E7 A7 `$ @ J) z! ?, k" d
1448066 SIP_LAYOUT TECHFILE Using a script to export technology file from Constraint Manager crashes SIP_LAYOUT$ W0 Y( G+ V/ r9 j; X, Y# y- O( Z1 A
1452431 CONCEPT_HDL CORE Obsolete $PNN is remained in a dcf file and Attributes dialog! H% S, M2 k0 h8 Y8 f+ G, x
1452640 ALLEGRO_EDITOR OTHER Updating PCB Board file concern$ K: o5 T2 R" V6 @1 J& b: ?4 C$ \
1454730 CONCEPT_HDL CORE Zoom/Pan Disrupts move and copy; Y0 Z8 n$ b- C" o& o5 D$ g
1457713 ASI_SI GUI Setting Sigrity_EDA_DIR for Sigrity 2015 /OrCAD ERC
2 q1 M/ p3 {5 Z0 G1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties0 ^3 ]- Z( |- U* Q+ ^7 ]9 ?
1458461 F2B PACKAGERXL The pstprop.date file "Conflicts on Net Synonyms" are NOT reported as errors8 D, Z9 P4 t# i G+ [
1459153 SIP_LAYOUT OTHER Mirrored components with pads on diestack layers (above top/below bottom) display on right layer but aren't selectable.
/ c7 X0 o4 p& Y2 u. P1461553 CONCEPT_HDL EDIF300 edif300ui writer crashes on ADW design
2 e( u4 D8 T# ?2 c1462254 ASI_SI SPDIF Ball properties are not translated to XtractIM using SPDIF
9 {3 Q X8 u+ D- @, x1462441 CONCEPT_HDL OTHER Pin text alignment and overlap with symbol boundary issues on symbol rotate. m x1 [ m" q' z* M
1463333 ALLEGRO_EDITOR INTERFACES PDF created using Export > PDF shold not zoom to Page fit when selecting another layer# G4 r( `$ P x' a
1463358 ALLEGRO_EDITOR INTERFACES Color assigned to pin not passed to PDF) X. [; U8 ^: t& ^! k# w
1463648 CONCEPT_HDL CORE Need ability to block the uprev of a design4 o* }+ b! o2 e9 w; _5 e1 l
1463839 APD OTHER Changing DIE property to another layer does not change its masking layer0 v. m1 z2 m1 r
1464380 APD OTHER Why pad at wrong layer when we place SIP 16.6 but 16.5 is correct.! W9 |' o2 r" A
1464660 CONCEPT_HDL CORE Problems with "save hiarachy"# P0 T4 Y' X# {5 s) m9 x! x
1464771 SIG_INTEGRITY OTHER PCB SI crashes when extracting differential pair topology from Constraint Manager# j% v) [. ]2 X+ C7 H
1464909 APD WIREBOND Bondfinger drifting off of the WB guideline% \8 a3 u: v5 C& \. F
1465273 SIP_LAYOUT STREAM_IF Streamout with mirror makes die symbols not located at where they should be in gds+ B- N4 u0 B- n% }- h# k7 N, R* P
1465457 CONSTRAINT_MGR CONCEPT_HDL Layer characteristics from a lower-level block are merged with the higher-level9 y* X3 |* b$ [3 B3 ?
1465541 CONCEPT_HDL CORE CM_VALIDATION_ON_SAVE is crashing DEHDL on startup
5 ~2 {3 _, x" o; F% a; ^7 u+ [1465543 F2B PACKAGERXL USE_PACKAGED_NAMES is crashing Export Physical
/ G7 B% F) ]0 P2 m* q1465911 CONCEPT_HDL OTHER Question about checks made in HDL while creating BOM
% D2 v- k: y7 v0 o2 i1465916 F2B DESIGNVARI Issues with variant management in ISR 055 #1 - Must save variant in Variant Editor to add info to CPM
- b9 k' |1 X9 D" X7 q1466230 CONSTRAINT_MGR UI_FORMS The Clear option is missing from the Reference Electrical CSet field in all workbooks
5 X- W( U! J# t- b# N `; y1466404 CONSTRAINT_MGR ECS_APPLY ECSet mapping using tags not working; b- |( D8 }3 {
1466492 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Add Connect command
# a4 a- l5 K0 w, b/ E1467156 F2B DESIGNVARI Out of sync endless loop
1 e' L/ U5 ?4 ~; |) ^3 u3 m4 Q' u1469062 ALLEGRO_EDITOR EDIT_ETCH Crash while performing neck mode for Diffpair4 \+ f- f1 h, P y0 \3 Q
1469081 ALLEGRO_EDITOR ARTWORK Short in Gerber Data due to wrong cut out around via$ E# p! U" O) h& y \5 c
1469713 TDA CORE Updating project with non-existing variant crashes TDO
7 o: K. X- V+ m. K. a
( ^( r, ^2 Y( h8 o) z) q- z* v# w正在上传文件中，分享链接稍后。。。。。。- J6 i6 j. d! q e* X
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发表于 2015-9-13 16:53
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