|
|
DATE: 02-13-2015 HOTFIX VERSION: 043* m" t& w1 s$ p4 b6 \
===================================================================================================================================
; h! G9 j* Y1 C7 U0 \3 [/ d1 h3 _CCRID PRODUCT PRODUCTLEVEL2 TITLE! W+ t3 F1 m9 E1 K& z7 \* t
===================================================================================================================================1 E4 h; e* r" S0 Y
1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW7 f& x+ A3 A$ t& L- n5 Y4 |( q6 d
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected
$ z+ l' B' ]/ M& W0 d5 X! U1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.8 }$ V' _0 T5 Y/ Z8 v9 F" g9 C2 W
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window) s9 |( P* d4 a) o! l
1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error* Q; O$ A. q% R7 z, P, m
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference9 B. ~2 \: P3 K8 e# t+ Z
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
' S, F1 z4 f0 B3 b* u1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols
8 d' \9 [+ t! w1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent1 E. ]& N' m% F
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.
1 W9 `, j( V+ y/ L5 A2 I$ ?1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM; A' h5 w: H/ H" f$ b W( {9 F+ K$ T: |
1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors# @0 R2 v+ T1 Q- S0 _1 u7 `
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
, i& ]* U7 w' l. M+ [0 d+ W1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes. g% _! M* g& R
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design9 V) K1 S) k. f# I+ W) |. E5 B3 C0 V
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers8 r+ R( l1 ~+ R+ o/ \9 [! }" E( ~
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
" x( N" N. M# j* e. M7 x/ y9 W$ F$ d1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
g" R7 K/ _8 z. `& P, K1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape9 e( S D# i- R8 E0 I
: `/ _: y$ V% k. j" m8 [
DATE: 01-30-2015 HOTFIX VERSION: 042' P1 D' v8 E- }" Z- C+ q, X7 G
===================================================================================================================================4 c1 F' X8 T# i3 s9 ]# V
CCRID PRODUCT PRODUCTLEVEL2 TITLE1 ~7 A) \- G4 d% K- x
===================================================================================================================================
' X5 V' Z4 d% u; N, @1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines# m# n0 O- H$ o @0 p; \
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run, Y7 J) V# {& @
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
1 E* a! j6 R$ {! S1349849 CIS OTHER Capture crashes on generating variant reports8 L1 ?: ?4 s4 ~ ~
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec6 u! X" ~' H# e: w
1350477 PSPICE SIMULATOR RPC server is unavailable
/ W- K& _) q# T1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
& Y3 z1 [6 R+ ~7 m! o1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
1 A/ w: o H+ \" g# X# K3 M; ]4 {( p1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
) v, I0 w; T" ]7 j" X+ v1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
% U$ x) H( C7 t9 ^% v. s1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
' K) _5 N( |: n1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
" V5 n1 g% l2 F N* q1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to: Y: A3 V, P' _( V4 v- S
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly5 G' U- i% ]! U7 ~
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
9 K- H/ Y$ ^- s$ W; {( L1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.$ X- I# A9 K6 Q; P
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design- K8 W! `) X3 @: D1 u' ~1 [
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
, I3 v6 B3 G1 Q* m2 ]% x2 g- h1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.& R9 \1 i( e+ V9 _) x
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
' |. a2 M( [3 X n6 W2 J- n1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
5 K# J$ a5 M( W* e$ }3 ]
- o" a) t. _) D; Y5 G1 P |
|
/1 
发表于 2015-2-15 23:37
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
