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DATE: 02-13-2015 HOTFIX VERSION: 043& u8 v5 Y5 T. r# `6 s
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q9 E- j$ D$ G2 j, }: WCCRID PRODUCT PRODUCTLEVEL2 TITLE; M2 v' g" ^( V2 y( J
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1 L, }/ w, v9 ]% S1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW9 P' H' O, k8 \1 X3 b$ |# c# T
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected, {' e) f2 n" J3 U/ x7 n* v9 l
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.$ u' s5 v4 O7 B" T
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
$ u' ]7 Q# B, V, R1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
: J& b+ t% W: W% d1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
8 w {: ~$ q4 G+ ~" |1 r; j1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
6 o5 y, ]+ A5 C2 W: Z9 W1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols+ C, R4 D& Z, S6 f& D7 I3 F1 }
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent0 n" S4 A: x8 k* s
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.( ~% G- [) }# y: I' j3 {3 E
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
% D+ P! D0 W% u. k6 g1 W5 s: M% d1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
6 T' }2 P3 u+ V) |% s9 S7 o1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
1 T8 S, X- @! S6 W1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
, b. U, D. @, P* E- y3 S1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
. u) O( H$ p( h1 a; ]1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
- Y8 @) m+ l$ r2 _% \9 m+ V8 g. Z1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design* \" O. ^' W% Z; x
1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
* Z- G% E) D4 ^1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape1 D9 {( Y8 |4 e5 ^6 X" L& A
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DATE: 01-30-2015 HOTFIX VERSION: 042$ X5 l( p: N3 A! V' ]
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7 t9 _& C' o- B8 f1 L" vCCRID PRODUCT PRODUCTLEVEL2 TITLE( s" n" Q" @( k
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1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines" |9 e/ w5 m' H5 r9 d. H2 G
1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
+ O! T/ c4 P5 C. x1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.: {9 b/ R" R# N( k2 p
1349849 CIS OTHER Capture crashes on generating variant reports5 O8 m! v! ]6 n) r2 m0 p/ a1 r
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec* i5 h+ Q0 x+ x p( L
1350477 PSPICE SIMULATOR RPC server is unavailable9 p: M: a* D9 h# S* t- n8 n
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash7 Q4 I: U+ \" |. |6 `
1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
- b4 U7 _; J2 u; h1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
6 N% q, E9 H* i2 \1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
; x- r+ |- F I6 E X5 N. T8 {1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase2 i6 V- \+ V. H; f. ]4 O
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
. c$ {* h c& R2 d: m" c* `) r1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
) z; K' V- S! A& p1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
% [! n) N. \9 W6 R9 E: x' r' r5 Z1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.* x) P5 w9 R" i" |. N$ W/ o
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
3 Z m7 w4 N! h* s1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design% K' }- L+ R `: M4 l$ @
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
. V7 [" y5 }7 H( v& D1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file." s; G7 X0 Y7 D
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.( F% O! p% q% f# m
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.8 |! o& Q s8 v" v4 t, I
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发表于 2015-2-15 23:37
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