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本帖最后由 auto1860 于 2017-7-3 15:25 编辑
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Fixed CCRs: SPB 17.2 HF0227 o4 O2 c- d K) o7 R
06-16-20170 e7 a3 z7 U1 D$ u- \- w/ V) ?
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CCRID Product ProductLevel2 Title
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1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
) ?+ Y4 U+ O& o$ c. C1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager1 @. D. `. E; O
1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
0 m' m) I- A. R; i+ {* \4 ^- u1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
! R$ U5 M% g; ^: j0 o1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
: D# x. S3 W" V1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager" k! ?/ |" ^: N& x. R5 o8 d2 z6 L
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
/ E" ^# {+ W# H1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it+ M2 n/ I0 R* W- I+ m; o( V- ^
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened/ S& K9 a: k7 Q
1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor
+ U! n2 l3 r* B' V3 f9 S1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints+ ]( E! A2 S& v; c: h- @' \3 ]
1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
: h' o% k1 z2 U4 W) d D) V1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
3 q) S& j! d; D' k- {8 g4 G6 ?1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.4 x0 z/ @# S: l8 U4 V
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run. y' D) r2 o8 V' n x
1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
; {7 Y- n3 S% l6 w' ?4 s1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture$ _6 Z' ?4 U' g# J7 n6 j1 _
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
0 S9 v2 I- N: H9 W1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic4 n B9 o' e' P7 k1 T9 J2 |
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic& E* ?- H3 I: d" h5 {+ K4 W
1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails! `! z; q9 u2 Q! h) [0 \( K9 w* f5 g! H
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-20167 Y, Q9 y& |% H9 I6 L1 G/ M
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor6 V7 u# ^ f: R; ?4 D8 F
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
% \; |- E# G: A) P" ?1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
1 p; ^& p( G N1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly/ X! {" S- u* B' B
1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point$ ~& A* L3 I0 t( n
1727206 APD SHAPE Merging two shapes results in an incorrect shape
' T G N) X6 j: p( Y$ C5 m1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL+ Y* f" O6 b& x
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic5 Q+ ^9 b8 ~/ ]
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 n9 ], M$ ], [( A' V) T, K
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
1 b0 q) Y$ K+ ]$ t1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
+ t x$ |( C; T7 L1 ~& B1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting" {" j+ M& e% V( W* {
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
n. w+ I) m. T( k# Q- {1719105 FSP GUI Tabular sorting not working in FPGA System Planner
6 k* T. l4 m1 }/ x1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor7 n0 K/ r+ ^* z) T2 Q3 J
1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file
( {* h/ k. @4 p% X- t1 K+ @2 w1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window( Y* s* J0 l8 d+ _5 A" u. W. l" F
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files/ w. s1 v, S2 f
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check ?/ {, a) n. }/ g4 i5 t$ g
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