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本帖最后由 auto1860 于 2017-7-3 15:25 编辑
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Fixed CCRs: SPB 17.2 HF022
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CCRID Product ProductLevel2 Title7 g( c, M9 O( p9 o) |- k6 B
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/ t- @( B4 e& w2 J# H3 Z$ d0 ]1 l; ~1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'' }+ T9 ~$ l8 E
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
0 R, d9 J# R( p7 t3 X1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager1 F/ m! t8 { L. A! S( r
1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager
$ h* A; s, h% h4 w1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications; c* `, p/ Y7 C* E
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager
! L3 V. O2 e$ }! m' q5 G1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor* d- v$ v" P, n" r0 w9 B7 d
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
. k0 k* ?- r# ~7 O$ H7 h8 ^7 z. | ~1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
# ~) r( W) i4 x+ p* _' T( t1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor" O" Z& `0 Q3 s* F- D; M& C& u* ?
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
( `7 F3 O% M, E p+ R# |$ ~4 [0 C1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps, M9 t/ [: L, E( o
1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
$ i! b* U- ?! m L, v; u" R! z1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.
% z9 K4 P f: B6 D9 D1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
' O- \7 B. K. W3 X1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor" F2 e& h; z- S6 X
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture" a/ _$ }5 R% s+ E1 A1 N* x4 E
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
V) a8 p y! ~1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
) x' [ G" I' r& }0 J' M1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
1 U( n' E6 Q5 y' Y2 s6 K9 _1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails& F9 i4 C: e+ J( s# r
1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016# j2 e1 U0 Q% J9 ]( H
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
- Z3 q2 l5 V. |3 W! U1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias
- z+ C" |+ w# Y- @1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
9 T/ p& F' y5 B9 m2 k5 I6 w1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly# u) Z3 R; Z- L
1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point
3 N' L% o+ H) W" t; |1727206 APD SHAPE Merging two shapes results in an incorrect shape9 \1 T1 E3 R3 L
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL2 U6 U9 Q9 ~% q6 @
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic W3 X- X. Y% w1 Q
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)6 y% X4 P- J1 V$ b
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
4 E% a& a* K# h& r# Q; H$ N1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option
. s' y' V" G+ E. ]% n% s! g& ]. T1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
; K1 C* s- |& w! S1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window. W: I% ?( E9 W# C
1719105 FSP GUI Tabular sorting not working in FPGA System Planner
- e. p: X; m+ P- e. q3 Y+ q" f1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor6 Y* y+ f2 H& j, u
1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file; w: R( h( Q( p% m+ d: f5 P
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
- @0 h2 y$ ~. h. e) C7 M: Y1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files
( D' M) n* t2 N- i) P1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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