|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 zgyzgy 于 2015-9-13 21:16 编辑
$ D l* q* e7 ]8 M3 ]
# ~ l3 p5 U9 v' J' e. CDATE: 09-4-2015 HOTFIX VERSION: 057$ c- o- g# j! T# C3 H+ q. a! r% _+ l
===================================================================================================================================
0 z4 j8 Y6 Y! a1 Z. N8 G) N! d" {CCRID PRODUCT PRODUCTLEVEL2 TITLE
' {2 |/ h. f7 q8 J; ~===================================================================================================================================# t& ~: B! ^4 ^$ ^
1249604 PCB_LIBRARIAN LIBUTIL Libexp verify runs both con2con and hlibftb8 | I# t6 g7 {5 J7 A
1417327 CONCEPT_HDL PDF Omit mechanical page while printing PDF5 M/ K, S& B9 C/ L- `1 k8 x
1440484 CONSTRAINT_MGR CONCEPT_HDL existing pcb diff pair name is changed by netrev! u/ m' Q: r. y: v! W- s+ Z6 e1 S
1441086 PCB_LIBRARIAN OTHER Cannot delete pin & added pins change after save0 Q( M9 o& `) b# o" ~2 C, c9 n
1448066 SIP_LAYOUT TECHFILE Using a script to export technology file from Constraint Manager crashes SIP_LAYOUT
& X; G6 Y& ]5 q, o1452431 CONCEPT_HDL CORE Obsolete $PNN is remained in a dcf file and Attributes dialog
- ~8 P7 F; d) {% ~. {2 L% z1452640 ALLEGRO_EDITOR OTHER Updating PCB Board file concern$ S7 \' ~' t; n% {
1454730 CONCEPT_HDL CORE Zoom/Pan Disrupts move and copy" Q: Z' v2 |; y/ p i; k
1457713 ASI_SI GUI Setting Sigrity_EDA_DIR for Sigrity 2015 /OrCAD ERC5 X Z2 c- u, i! g- q5 k8 A
1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties7 m. Y. z3 l* G, w' B$ _/ W
1458461 F2B PACKAGERXL The pstprop.date file "Conflicts on Net Synonyms" are NOT reported as errors- k- Y$ p+ C$ N( G6 y$ h# h$ f7 q
1459153 SIP_LAYOUT OTHER Mirrored components with pads on diestack layers (above top/below bottom) display on right layer but aren't selectable.
, `8 x2 Q5 u) @& {$ `1461553 CONCEPT_HDL EDIF300 edif300ui writer crashes on ADW design
) P* ?8 S3 Q3 ^) S+ j) d1462254 ASI_SI SPDIF Ball properties are not translated to XtractIM using SPDIF6 ?/ M" ?- R+ ^" J
1462441 CONCEPT_HDL OTHER Pin text alignment and overlap with symbol boundary issues on symbol rotate6 v8 |8 q% K9 j0 `9 K
1463333 ALLEGRO_EDITOR INTERFACES PDF created using Export > PDF shold not zoom to Page fit when selecting another layer& h( |8 `9 _; i
1463358 ALLEGRO_EDITOR INTERFACES Color assigned to pin not passed to PDF0 h! P" ^/ q1 I- i8 @. Q1 X
1463648 CONCEPT_HDL CORE Need ability to block the uprev of a design) P, p5 _3 c; H8 F
1463839 APD OTHER Changing DIE property to another layer does not change its masking layer
# [1 b3 J) s0 \: s( n) W1464380 APD OTHER Why pad at wrong layer when we place SIP 16.6 but 16.5 is correct.( Y% h7 q) h; P
1464660 CONCEPT_HDL CORE Problems with "save hiarachy"
" d/ o- O" X1 J6 z9 F. b- }4 X1464771 SIG_INTEGRITY OTHER PCB SI crashes when extracting differential pair topology from Constraint Manager# z1 e, \% [! J+ Q8 u6 O0 x& P
1464909 APD WIREBOND Bondfinger drifting off of the WB guideline, l* D% W1 R- P' L4 O/ g
1465273 SIP_LAYOUT STREAM_IF Streamout with mirror makes die symbols not located at where they should be in gds0 |5 A' Z+ [, w; X7 x% D) Z3 v" N
1465457 CONSTRAINT_MGR CONCEPT_HDL Layer characteristics from a lower-level block are merged with the higher-level4 a6 q, E7 q+ A6 U- h
1465541 CONCEPT_HDL CORE CM_VALIDATION_ON_SAVE is crashing DEHDL on startup+ f+ c3 f# `9 w6 y& U9 y
1465543 F2B PACKAGERXL USE_PACKAGED_NAMES is crashing Export Physical
' r+ W0 b0 d, t. T$ _# J6 z1465911 CONCEPT_HDL OTHER Question about checks made in HDL while creating BOM
4 ~1 _9 _3 _3 j, O! C1465916 F2B DESIGNVARI Issues with variant management in ISR 055 #1 - Must save variant in Variant Editor to add info to CPM
7 j0 |# X d: p+ ]# |- g6 I1466230 CONSTRAINT_MGR UI_FORMS The Clear option is missing from the Reference Electrical CSet field in all workbooks; i% w6 w9 B% r3 i
1466404 CONSTRAINT_MGR ECS_APPLY ECSet mapping using tags not working
7 j% K8 h' {, G1466492 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Add Connect command
# f* A4 F" V8 Q( N! \' o2 w1467156 F2B DESIGNVARI Out of sync endless loop6 g) l3 u0 W5 g7 V: w# t
1469062 ALLEGRO_EDITOR EDIT_ETCH Crash while performing neck mode for Diffpair
3 H/ C/ A4 P' c; ~* y3 ]. p1469081 ALLEGRO_EDITOR ARTWORK Short in Gerber Data due to wrong cut out around via* S# b d3 T4 h0 s; V
1469713 TDA CORE Updating project with non-existing variant crashes TDO" A' k- A# ^+ q
0 @: C% c! a# Z, Q' R
正在上传文件中，分享链接稍后。。。。。。
1 e5 s# c. n5 s& ~6 J, q9 Z5 x9 t, r% e
http://pan.baidu.com/s/1qW3jhoC3 p1 Y* M( P; V) }: O0 V
|
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2015-9-13 16:53
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
