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DATE: 02-13-2015 HOTFIX VERSION: 043/ c' k! H9 g9 K; d9 `
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
0 m- N5 d c8 j8 I0 k===================================================================================================================================1 e' i# e, V; J3 ~: `) D5 D
1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW0 v/ m+ c' L! r+ H: E
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected( I1 B! [- v9 ^+ Z% q- {
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
( I% q8 Z D' ^# r# k8 G1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window8 G( m: |* H# P0 h
1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
" ? c3 d3 q7 y$ @3 O+ r0 F8 s1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference+ g5 A( F, Q P" ?
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs9 [; w3 ?4 G2 G, {* M+ S+ d
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols
5 c2 F9 V& C8 S$ Y N, U1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
% z( w* a* @- ^: X' g& }7 g1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.2 {" i, A+ p G# x8 R
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
) U3 H2 W2 Q4 s+ {" X3 T1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors* f4 f8 I' f: o: j
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete$ x/ o% k( i: F1 }1 F
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes) T% l* |' E- _7 r6 v8 W$ d
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
0 N. @$ c- ]% v/ s1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers( U3 B% i* g- `8 [
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design) z. G$ Z2 w3 P, [ b
1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
; L/ O9 a, u5 U. K1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape
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DATE: 01-30-2015 HOTFIX VERSION: 0423 T! g! y9 `7 p. G9 p
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
" ^ t. l1 d5 f2 S4 Q- A, N===================================================================================================================================# T. _( n' J' y$ P
1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
8 p$ {: M& S5 R O1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
4 K" O M( M* G! {' r5 G5 l: ?( H$ I1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
4 |2 O5 ?1 m: y& \( V- g+ a1349849 CIS OTHER Capture crashes on generating variant reports
9 F# W, g5 _0 H3 k3 k+ R1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec Z1 C# L5 c' o- w N3 P& i/ G
1350477 PSPICE SIMULATOR RPC server is unavailable2 H0 q: O9 A5 D3 [5 U: H3 s$ J
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
! y* Y: p5 s2 g1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property' K7 N& D& k4 F- f9 ]
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.& D; y0 X# |1 j# k2 N |
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers; P" B3 d4 z9 B1 q
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase+ ^6 E) j# _7 l8 F
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
2 ?; ?, @ A! o+ p' F1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to9 `8 F8 ^0 |5 U+ L( s
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
9 T* I( x/ F$ b$ F* @% e' u1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.3 P$ X# T+ S$ H0 u: y
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.8 r. _& H [2 ~! U& ]5 h3 c
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design! G' r- F7 B- ?# G6 L5 O6 d
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor: c- W% |. W9 Y* a$ E3 `
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.- d8 n0 I/ O7 B: n
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
& C, C7 ]4 s( H1 W5 ~/ B4 l; N1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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