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DATE: 02-13-2015 HOTFIX VERSION: 043
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CCRID PRODUCT PRODUCTLEVEL2 TITLE; ]& O" O8 L. W9 D5 w, {1 p4 s
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$ L! C. O; S5 p" c1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW
& r! o9 X% D5 {6 e8 P1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected: ^' F# u' P0 r: f# M5 U7 V5 A! E ^) d
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
& O3 f$ E8 U" ]$ k, s1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
/ M, {; j! I2 |' _1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
% D, X3 y6 o" j% a4 k# a1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference% R( n+ P, T+ [: l" `
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs9 G N5 P( P3 C1 r" {7 U
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols7 s) o3 \4 X+ a" q2 q! a
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent3 g) P2 t" K* A8 @3 e4 ^
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.+ u# ?7 W) E) u+ u, y7 Y! I
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
$ e( Z" P3 k4 `3 x0 E$ q& \1 V1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors% D) @) Z, k1 a) X
1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete/ k( a9 @2 N# m- }: g+ j
1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes4 W. K2 S5 i' A0 P- q" k- W
1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
" w5 k2 e( o% E6 r4 B' O1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers
/ z( `( c4 e8 g, t1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design# e, X- d3 X8 z0 c# W4 X
1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
; R$ L0 V* a5 g1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape5 W" C6 c- g, q, @( ?( m
" S% x3 a8 w6 iDATE: 01-30-2015 HOTFIX VERSION: 042# a3 X$ \" U U# U
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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. n. u5 G) ^& @! Z; G6 z2 Z1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
5 u: a5 w& S3 u) U$ i$ ~1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run- K) J/ ^& c( G x: e1 Z2 q
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.+ a2 @7 s" y; \/ `; M
1349849 CIS OTHER Capture crashes on generating variant reports
3 U) T, z. M& L8 c" l* q1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
; a* g" e i/ r" t- J/ Z1350477 PSPICE SIMULATOR RPC server is unavailable
, w( O+ Q6 Y$ i2 l# h) ]1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
$ F8 o) h6 e: B' J1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property Y+ c8 `) \+ u3 A, J- H
1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.) ?6 A9 O$ l, }4 h- |
1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers# t9 U0 i j1 P0 W" \3 Z
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
" F* W# F0 ]9 q0 T) E1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs./ x- O- _2 E7 o7 u9 R) W! ?
1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
$ r Z, K- Y* V1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
( u2 G: v! p- ]/ S. ^9 a1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.4 l1 B0 p2 R% e) s) O+ V
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.& T% q& f# r6 o" A" [
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design' b4 t4 }+ p. \$ w8 ^. c
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor' k! v& I$ X: h B' s
1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.' R) Q! p! H% W! h/ ], }
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.0 R: k7 |1 @. r
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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