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本帖最后由 auto1860 于 2017-7-3 15:25 编辑 - V' z# Z6 P& K5 E( e
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Fixed CCRs: SPB 17.2 HF022
8 E& ~: z( q0 A w6 Q8 D06-16-2017
; {/ E2 C0 ]( P2 K% o' [+ G f( i========================================================================================================================================================
; ~$ g- `1 R Y3 z2 uCCRID Product ProductLevel2 Title
1 Z/ {3 @$ _7 ~* S _========================================================================================================================================================8 v9 ^9 N$ z$ d! |9 r
1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'( Q$ J; M6 y5 U; C( r! q# ]
1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager+ Z3 q2 B0 S0 P8 c; I
1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager; L# i& N1 Z+ A& `. q! f
1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager% a4 d& \) P0 C1 r
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications* z6 m4 m5 }- V4 Z( x0 N1 P& `9 l
1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager+ W0 |; |0 ] e/ M: `$ J( Y: x
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor
; L! s- X5 r: q. y1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it
! w8 _% d! z, B8 I' c; E& v0 i3 ^1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened
8 m0 l) a% q5 h" Z8 e+ j1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor$ {- g* Z! Y; l% E
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints
* J: p& v( K% i7 ~4 s1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
! t0 [% s8 }; b% V) B! M1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position6 o4 Z$ U l( k
1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.
5 \9 P$ V. l# U: {- W: k7 v1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
) ?# U6 j7 M6 Y: L, s J3 ?1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor
1 q) h0 C+ V" ~; _' N. f1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture6 W7 u- j* `1 [3 l
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
8 i6 @3 i- s' I% l8 t3 a+ L6 e& s# B0 ^1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic1 g) m- z2 y% H0 E1 \
1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
4 y6 b3 }2 `. ~4 l- |7 P1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails
% `" U; I! E' s- t" ?2 `1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016$ v# S, [, l, x# R3 x
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor9 h( K0 z7 t7 t8 G" w
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias6 b. @& j6 P6 y# C4 R4 f2 t
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-20168 m, q+ z. X& u& l
1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly
" k2 @2 \5 i4 {4 v" @! m1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point# y- P1 E s& m' A6 T
1727206 APD SHAPE Merging two shapes results in an incorrect shape
- m) ? n% f b5 Z- v) e1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
' x5 h, c: L& C9 a/ {1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic5 b' K- y* B2 B! {+ m1 I
1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)
+ f; m0 T% X' j; w' }. b1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
5 t) d2 S& `: ?% S v7 v1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option* z! l+ Z1 Z" T& H f) M
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting3 J& S1 h% v% n9 `$ i; g# {
1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
, k L: c q" H1719105 FSP GUI Tabular sorting not working in FPGA System Planner
0 E9 t' ^, b; D$ O1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
% U. i' \" ~$ l8 F1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file/ ^' n! u5 ], a9 T4 L- W, e% }& g
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window! O& ?$ H7 d7 V: s' V; a1 e
1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files. x: h3 Y9 E# K$ F. C1 H8 b8 e T
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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发表于 2017-6-29 13:23
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