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DATE: 02-13-2015 HOTFIX VERSION: 043
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6 i2 V& D$ a3 a8 q2 Q3 Q; Q/ D5 ACCRID PRODUCT PRODUCTLEVEL2 TITLE
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( H) l- G6 \3 w0 q. ~, l) Y* h- }& m3 w6 a1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW4 m' R- @4 Q6 d
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected# ]: n! l/ E0 F2 {; j& z
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.8 z- B. A; m& r+ }; Y4 U& q
1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window2 z( e' o% h! `$ Y$ y
1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error
2 j8 r b: z5 i1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference* J8 Y9 e# U8 a- {# J, A3 h
1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs: L1 G" m8 m: M+ E* r. s
1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols! u; V, p& y! e! U" i0 @# d
1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent% ?$ y0 Q, N! N2 c- y6 q
1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.! r2 q x5 z* f4 `
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
, \/ E2 D' M, p: a4 ` h' n- `7 S1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
8 A2 m) D# F( \! c1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
% v+ \' ] f" N. ?2 T# X1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
( v1 G9 f( y7 i4 B0 E8 w8 ^1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design
# m" |0 l: r8 v, {1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers* k- k- Z+ e" @3 d9 r
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
4 K% S: R6 ?+ z7 G$ p% T1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file
" f& N) C0 w* x( `4 @3 n6 o) F2 O1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape, y0 E9 ^' S) v5 o8 e
) _8 u& q7 ]+ }$ GDATE: 01-30-2015 HOTFIX VERSION: 042
2 z& W% a; g9 N! f7 F1 ]& j6 u===================================================================================================================================
2 ]6 h( j, t; S' c9 l) `CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 }1 g6 h* Q* i, T( x===================================================================================================================================& c; U$ }8 ?, v6 b
1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
" y" l, ]5 b9 z4 \, I6 H( e! U1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run
' ~, k% l# H8 Z; h+ V, _' [% f; }1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.- @2 q* ]4 _) y: r [+ @1 @
1349849 CIS OTHER Capture crashes on generating variant reports
, L0 \; Y" R0 p# c2 U8 J; B1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
0 t3 e2 y V [1350477 PSPICE SIMULATOR RPC server is unavailable
; K! H6 O& W$ Y" M1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
7 g2 ]6 X, R8 b& |; A1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
" ^8 z' b" P' P3 G# \6 M1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
; B2 v. H7 d6 h. W& V1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers
D/ E9 k& Y7 b! c1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase% _ \& `0 u$ D! _+ E6 Q: s
1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
7 j- j% G3 b. L6 ?0 L0 r1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
/ [. ?, l( C; V4 r7 g$ }) Y1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly5 K- ~% s0 F T' m7 M
1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.
" s2 M0 i+ O+ N3 L% ]- i; J1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces.
( C# O, y$ b$ s3 U! J1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design: B) Q: O9 Z! k( L# ^( [
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
2 e, g" ^ ^" k& ]; S2 D1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
! ^- r! z6 _4 [, X$ I8 x) z1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
: r0 S W3 r- \- F1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.+ Q# r8 G( R% ]5 u9 E
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发表于 2015-2-15 23:37
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