Cadence SPB16.6下载(Hotfix013已发布更新)

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Cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
http://dl.vmall.com/c0ych9k8m3
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DATE: 07-26-2013  HOTFIX VERSION: 013
8 C8 U0 N- S, r; K" _% W( V===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
: ^, j- E% M) `. t; Q2 B' t- i===================================================================================================================================
111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
( m# [9 ~$ Q; W) b. l9 a% t/ k8 t186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
" l0 S/ k$ _3 _: R+ h& N583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
' k- T3 v* o* y1 \% `, `801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
+ y2 j. |" a( b6 z# K  F813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
! R! ~4 u# S) f881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
1 }# [" C, U# l4 _/ H887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
6 E. e, F$ O3 j5 N$ M911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
( r" R* X/ _5 Q) h8 ^1 o; Y1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
% z  X, ]* q- S; |5 W4 m5 I1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
' H, `' ]$ {0 p& K4 `. d1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
: M( u5 l5 `/ v: s6 g+ `- Z1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
6 Q( J1 i3 O  d( w% m0 i( l, S1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
- Q( ?( U0 i" ?7 D1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
9 [1 ?4 }! H2 C8 V& K1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
3 F3 ^7 z% F  g3 ?) p/ E" |1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
- O# N/ T& q3 X1 R, w: w1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
0 g: r5 R- ^: Q! `: f0 I; w1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
  Y. Q% ~) H( q! p& D+ T5 D  |1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
, \- k" Q5 e0 _) V  H( X9 S1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
9 N+ S- R' \! n; D1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
7 ~1 F0 L/ T  W' {# ^) M1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
' _# B% L5 f5 @+ G: r) w1 ]1 f1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
+ E, g! S! [$ I: q& I/ F& r3 W1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            OrCad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
. h7 B+ T+ E: V" B8 O9 T1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
  Y6 r  Y) l7 w: h7 u8 r; i1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
2 }' n( u2 \# M; k2 V, {$ u1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
, S7 q7 |: P6 ?! S0 E; L1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
$ A+ }. d- a3 l( @' K1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
! G9 c  B( J# L1 D$ o" S( E1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
" u; M$ n. N" w! n( g" S+ F1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
  e* g! P  M7 g% M5 m9 w3 [! b* C1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
3 Z% L, a9 |; x1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
+ u* k; o) R7 `8 |4 R1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
2 Q  K1 K, _) @$ L! I# Z' e/ D1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
# H, X- g; G# A6 x1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
6 I; e5 X/ T! m2 Y7 s' N) R( ?5 P1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
1 U3 G3 A. s& f5 ^- N. g1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
: ?) ~3 ?: w( O1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
9 A+ b$ y) |/ R1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
9 j" _% x. u0 W5 S1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
3 r, r' q; b  h  n0 F1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
' h3 f9 G5 Q5 q# B9 q6 i) B7 q1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
( X$ F4 @* s+ P2 b9 F" o1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
- H1 \) l( Y2 K9 I1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
2 z3 x0 }3 b3 H8 ^5 P& m1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
$ r9 u  G" {9 @1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
, z( ~1 t( {% a* A. z4 M  i% z0 n1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
* `( s' v1 A  x! L; x. N6 X1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
" h: z; ?4 `7 ?( d* E- X1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
$ b1 @( g' j5 D, e9 e( `1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
% `  C! [0 x# B5 V6 _' P. p1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
( J2 }3 `$ F9 G5 b  N0 `7 u1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
7 M3 \6 D" |% d/ O+ \2 n6 o1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1 B1 ^3 V6 J3 ]1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
$ a  f0 }' v$ \1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
. `  k" f* Y6 i9 T4 D9 ?1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
4 Y% L! e! B9 q1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
# @3 _8 O' t; N0 I" v# E0 u; I1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
* v1 F( F0 L" a1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
5 e: F! K: B% F- _) _5 Z1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
, F0 x1 ~$ }! `& E. p) A* e" ?1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
& e: \( H/ K- A6 U  y: _: l9 U1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
! U' b1 z5 L' |8 `( T2 ^4 f1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
) g. y! d8 J9 Z, A) [1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
. C& m: I9 G% b( e+ Y4 O3 Z1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
4 ^; f% p" n  e0 ^! F4 x& o9 V1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
* ]5 {1 k7 |8 c4 V9 O/ s; |  l1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
+ H6 P7 ~5 e0 v& h5 i0 ]+ E3 `1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
3 F  `0 {/ |0 D" {! y1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
: a5 y; N& `0 g( u! I" n. r- i1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
& {4 B3 W2 N8 T' n1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
# B+ Z" @4 j) @2 J& I: J1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
! c! w1 t" m2 E5 ~. N1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
* G* l4 P( L( [, z1159483 PCB_LIBRARIAN SETUP            part developercrashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
7 r! Q" n. s! |1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
3 a$ `2 X6 L5 m1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
6 e3 `9 r( D6 ^+ u; C5 `) W1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
8 W+ z; D1 M. f  b5 c3 p) j- X1160537 SPIF          OTHER            Cannot start PCBRouter
, o$ A' T, c' U1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
$ `8 k1 {- @) I3 A1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
" N( g* J  H$ r6 Q. k* Y  h1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.

txqtomton

楼主辛苦了！ 谢谢
' E8 ?8 Y7 O* x

2000

楼主辛苦了！ 谢谢

q343408315

怎么屏蔽了

陈志军

好

每一天都不同

感谢分享