Cadence SPB16.6下载(Hotfix013已发布更新)

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Cadence SPB16.6下载(Hotfix013已发布)

2 A7 _& s  F: c% q" B& @Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
( \5 d$ v+ C& E# B) z. a, Qhttp://dl.vmall.com/c0ych9k8m3

  f% B- F  Q+ Z/ L0 d" ?" mDATE: 07-26-2013  HOTFIX VERSION: 013
2 }* x& P4 z' B6 T, @===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
! u' @0 X! P. I/ ^134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
3 {$ C) Z/ P/ X# j3 O186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
  Z" {+ k1 B3 H; A- ?3 d583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
$ u; g1 S# p  r6 R' w: E- `3 @) V7 ?591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
& D0 g1 _/ z, d( ]$ E801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
' e# {& ]" z" h5 G: `813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
6 L" k: h- C* P887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
: e7 ^# a; }+ }4 r6 n911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
7 W+ f( ^" }: [! A" u5 ^3 {+ w1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
$ U1 y1 b. p5 e3 b1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
  k7 P! {6 B4 a1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
' @: A4 d  C. N5 e9 J6 \2 {3 C) @1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
5 t+ {( Y! w# R3 F1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
3 M! g- k$ G0 y) P1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
9 h- |9 C3 ?/ K. G$ O4 ]1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
- ~& T: Y, R6 u1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
8 k* P0 t$ k  q) j+ y1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
! g7 d- f8 [  N/ D# u$ n" j1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
4 k! _& v/ ~% Z. D1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
. V1 w+ b5 `2 k- O* R! y1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
8 b* a4 b5 `1 ^0 u7 s1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
* E$ y5 r- f" U0 P3 d# |1109024 CIS            OTHER            OrCad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
' `: M% [' F6 V% L4 Q' v5 ^1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
4 E" M( M4 e" R2 \1 _1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
  D  \& e; G5 [1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
( l3 A; ~1 e: Z1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
9 l& A5 Z& ]; P2 g. b6 Q! R7 f1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
& _; `) [$ Y' Z; S; k1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
" }9 R& h8 L% P+ n* k1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
; i9 X5 X$ C) ]7 @1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
# y6 ^6 `9 A7 s( E" J) b0 G1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
; b4 }* \+ m5 i! x1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
8 F4 c( y# ~, }1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
3 \4 L8 ~* c7 G1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
3 a! d7 H% I- Q3 ^0 M; D1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
: y% m$ U7 h+ u2 [- G1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
3 F: o% [+ H, m, r' C4 y1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
/ X. r% \$ P7 ^6 t' I9 }8 K1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
2 m5 k' [. V3 R6 A1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
! j- U4 H2 _+ w+ ^5 L1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
/ W# b7 Q3 ]6 A% _+ G( D/ I1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
% |. E6 X; D" L1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
3 N- P: o8 W% |( S1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
6 q$ _. W/ ]8 v8 X1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
/ s* Z3 U% [& d9 V1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
' K" t3 ]. [3 x1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
& s4 d: D" q  ]6 K  N. B: E1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
- Z$ ~- a: v9 k1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
3 y# x& x$ w8 w. [1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
) ]; h  i  y; H0 [5 ]5 ]1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
6 N& d% s) j0 n0 ^) P, h1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
+ K0 k3 q& W$ J6 U, Q" o1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
+ u) k: E* w% [( p3 K/ _1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
+ H- {+ W# f2 C1 f6 N5 _" {! G  x1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
. m- ^5 ^1 U  `, P, q& g; y3 s1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
' w; b3 A6 [0 v# E7 }' L" U1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
8 h. M0 T3 h, ]  S9 }! `. B+ e1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
) |4 n- M4 r7 R1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
' j) H1 i8 s# i/ l- O; n) X1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
, Y9 k9 U" x+ l/ E1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
5 X: D$ ^7 W2 C) A. O8 o' \1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
5 M! d/ c5 L2 D' }5 n  Q4 U7 A3 a* K1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
4 u7 g6 W: ^- \1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
9 G% V. l4 G+ h0 Z' f1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
# c7 ?+ o& T6 j5 h5 d1 |$ r1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
$ I4 [- k! _% u7 {- S1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
5 T1 g* s+ G, i. c6 k1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
8 O9 N8 p8 B8 _4 G; y1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
2 s4 r- K: X0 t) ?+ N7 f1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
0 L( _! b( b( @" R/ T, U' K1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
$ |; X! m4 I7 N& e" ~0 w+ E$ d' L1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
* {/ ^2 ?2 S( C1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
. X! N6 f$ K/ e- K1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
/ A1 t/ A- B* O/ |& q: _0 x1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
  x. Y' j' F3 g& p1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
- H$ p! I" J9 U3 v$ b7 `1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
" G* X! a; B: ~: u9 j% Y1 s1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
$ d( Y+ X4 j$ r: s1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
3 E' g) J1 l9 y7 m/ H1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
, D7 |; f- C$ y5 k6 R1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
7 D* `! c9 J( h+ x# v1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
3 |8 w! d4 V* u7 R5 `  y! Y; `" c1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
9 L* @8 q9 m  F5 Q( M3 H1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
: H  O) ]4 O5 u, O4 O2 d2 }1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
8 e6 Z8 q/ E- R, n# ~7 A1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
- |& V4 @: e. T# h' S1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
+ o# {8 G6 U8 t+ {/ a0 W& R1159483 PCB_LIBRARIAN SETUP            part developercrashing with
0 C' t5 Y/ v* ?8 o# e5 N: J1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
3 b  U1 u/ [( T! `* {( O* A1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
) G+ I( ]9 A4 o; j2 d1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
+ }. n3 _  t# W$ Z, W. J2 o1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
, `- E; U; N" d! g7 U6 r4 `1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
; Y/ v: k) V) N/ f& ^2 G3 L1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
; m9 \, @6 U4 g) c# i8 P1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
& L$ j# S" V5 x" S1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
. z! n5 `+ }* b* Q3 y# v  ?1 ^1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.

txqtomton

楼主辛苦了！ 谢谢

2000

楼主辛苦了！ 谢谢

q343408315

怎么屏蔽了

陈志军

好

每一天都不同

感谢分享