Hotfix_SPB16.60.022_wint_1of1

steven.ning

http://pan.baidu.com/s/1bnpaZfD

sztyzhi

太快了，刚装了021

suiwinder

正在下载

yuxifeng

能告知补丁包的功能及解决的BUG吗？

steven.ning

yuxifeng 发表于 2014-2-11 10:38
9 ]" f$ l' d! d) B能告知补丁包的功能及解决的BUG吗？

我只是从EDA365网上搬运了一下而已，原来那个下载太慢，我把我下的转到云盘上,速度快，方便大家下载.更新了什么我也不清楚.

jsf120

找了半天，感谢分享

wolf343105

非常感谢steven.ning,祝你马年发大财.

nbxiong

等的花都谢了，更新好慢，跟看美剧似的。。。

steven.ning

wolf343105 发表于 2014-2-11 15:15
非常感谢steven.ning,祝你马年发大财.

6 T$ N# O0 U) |$ a1 s" z1 M9 @8 z谢谢，也祝你马年行大运！

steven.ning

yuxifeng 发表于 2014-2-11 10:38
* \2 O& S9 J  R$ ?! J  i- s6 ~能告知补丁包的功能及解决的BUG吗？

1 O( s2 p9 m8 Y0 r. UDATE: 02-07-2014   HOTFIX VERSION: 022
0 a+ n, [! L% O; @+ A===================================================================================================================================
CCRID  PRODUCT        PRODUCTLEVEL2   TITLE
1 m2 f. r* n4 U===================================================================================================================================
. R1 ]- H, W" L0 }' s& x192358 ALLEGRO_EDITOR PADS_IN         Pad_in does not translate some copper shapes
) V$ B% S" A( M( Q3 Y8 m222141 ALLEGRO_EDITOR PADS_IN          PADS_IN: Extra shapes are created whenimporting PADS design
274314 ALLEGRO_EDITOR PADS_IN         PAD_in boundary defined for flooded area be translated DYN
) R# y6 N" E1 h( N9 e  S413919 ALLEGRO_EDITOR PADS_IN         pads_in cannot import width of refdes.
& W. ^1 e! \- B- ~  v' R8 h609053 ALLEGRO_EDITOR PADS_IN         "Mils to oversize" of "pads in" did not workcorrectly for MM data.
1 x& U" q" s7 Y/ u" j* A2 p666214 CONCEPT_HDL    OTHER            Option to increase Line thicknessin publishpdf utility
738482 ALLEGRO_EDITOR GRAPHICS        Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
) Q1 V7 P% F2 |7 Z3 \982950 CONCEPT_HDL    OTHER            change the mouse button for thestroke to have same function with in pcb editor
, Z: n: s- {( r$ H' P( e. j/ z! p1020886 SIP_LAYOUT     LEFDEF_IF        a quicker way to promote die pins (byimporting macro_pin list)
7 F* ?7 X  f. t" Q  G4 h/ |1032678 CIS            VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.
# Z' j0 |4 k6 u: I3 O. F* G2 S1033864 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translates teardropspresent in design
1054862 CONCEPT_HDL    OTHER           Option to increase Linethickness in publishpdf utility
$ R6 ~, C, N( j' W1055252 FSP            PROCESS          Add a synthesis option to target agroup to contiguous or consecutive banks
. J* ]3 @: C3 K6 ]) @1100772 CONSTRAINT_MGR OTHER            In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
1135020 CIS            DESIGN_VARIANT   Variant list is showing wrong results forhierarchical designs
3 t6 ^6 h0 c2 f& Z) Q, B; n& {1138951 SIP_LAYOUT     DIE_ABSTRACT_IF  Fix die abstract r/w to properly supportpinnumbers on ports
) Y7 I9 O1 R' y% }( Q1140042 CONSTRAINT_MGR OTHER            Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
& N; a( t/ G( b1143662 ALLEGRO_EDITOR INTERACTIV       Enhancement Request for RMB - Snap Pickto  options increased to include Pin edge
9 T# J* s8 G8 G6 h  J# L' L1147961 PSPICE         SIMULATOR        Simulation produces no output data
( \  O# b0 \; \5 ?' w5 p% D! W1150874 ALLEGRO_EDITOR PADS_IN          Dimensions in PADS are not translatedcorrectly during pads_in translation
1154184 CONSTRAINT_MGR CONCEPT_HDL      Difference in the way topology isextracted in 16.3 versus 16.6
5 Y( Y- b0 @9 k8 O( r2 R1154770 CAPTURE        PROPERTY_EDITOR  Variant Name property doesn't show value inVariant View mode
% I# d$ E4 z9 a/ {1158350 CONCEPT_HDL    CORE             Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
. ~4 r6 ^8 f2 h% e7 s" ]$ V1162347 ALLEGRO_EDITOR EDIT_ETCH        Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
9 [  ?% C2 M1 k3 x! ~- ~1 w% g1165553 ALLEGRO_EDITOR INTERACTIV       Subclass list invoked from the statuswindow does not represent correct colors.
1168079 FSP            MODEL_EDITOR     Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
1172043 SCM            OTHER            : in pin name causes SCM to crash
1172207 CAPTURE        STABILITY        Capture crash while adding new partfrom Spreadsheet
: g0 |; _9 u5 ]/ G7 E: y/ ?% H1172743 ADW            TDA              Allowed character set for thecheck-in comments is too limited
1 r! p: K  T$ h; {8 G% I1174099 SIP_LAYOUT     WIREBOND         Option to reconnect wire based on 縫in name� in the Wire Bond Replace
1177672 APD            IMPORT_DATA      Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process
) W, _( I- Q4 q- U1177714 CONCEPT_HDL    RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
1177820 CONSTRAINT_MGR INTERACTIV       Done the Allegro command when attemptingto launch CM
7 N* \  Y- J' D2 Z: e- C1 C- F* F1178586 ALLEGRO_EDITOR EDIT_SHAPE       Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
1179688 PSPICE         STABILITY        pspice crash for particular HOMEvariable vlaue
. C: o3 R& j4 T1179827 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
1179879 SIP_LAYOUT     STREAM_IF        Data file corrupt when exporting Streamdata from SiP database.
; o& n+ a: V, p- W1180164 F2B            BOM              BOM csv data format converts toexcel formats
4 I6 H" q' {6 g" m1180477 ALLEGRO_EDITOR INTERFACES       IPC-356 output is listing a duplicatelocation in the comment section
1180932 SIP_LAYOUT     OTHER            SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
1181377 ALLEGRO_EDITOR INTERACTIV       Pick Releative does not work correctlywith RMB-Move Vertex
: s! I; i+ S& R2 @$ K' m1181516 ALLEGRO_EDITOR DRC_CONSTR       Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.
0 j$ \9 P; w( ~' Q; W) j* [1181739 GRE            CORE             Running Plan > Spatial crashesGRE
1181935 ALLEGRO_EDITOR DATABASE         Enh. Property that allows internal C-CDRC errors
1182185 SIP_LAYOUT     OTHER            SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
1182566 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap
1182599 CONSTRAINT_MGR DATABASE         CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
1182892 CAPTURE        SCHEMATIC_EDITOR Pspice marker rotationbefore placement
1183682 ALLEGRO_EDITOR DRC_CONSTR       Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
1185445 SIP_LAYOUT     DIE_ABSTRACT_IF  Die abstract export needs to be able toselect xda file type when browsing
1185932 ALLEGRO_EDITOR SHAPE            Soldermask in solder mask void DRC
/ i" d0 x0 Q8 ^) N% x, t/ h1185946 CONCEPT_HDL    CORE             Ericsson perfomance testing report5 sept 2013
1187213 FLOWS          PROJMGR          Unable to lock the directive:backannotate_forward
- Y6 r$ r# a4 _2 f/ R7 C1187444 ALLEGRO_EDITOR DRC_CONSTR       With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
1187597 ALLEGRO_EDITOR DRC_CONSTR       No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.
1187723 FSP            PROCESS          Synthesis can fail depending on componentplacement
. @8 L2 z$ x1 P% c0 O, z8 U1188164 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
- P3 s1 j+ |4 E; ~4 o8 z0 c1188245 CONCEPT_HDL    CORE             INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
' e$ t9 Q6 o7 z7 }* B9 _3 L1 Q  H1190927 CONCEPT_HDL    CORE             Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
( y. ~- M% @: E$ Z8 f  ^+ p- r1191497 ALLEGRO_EDITOR INTERACTIV       ENH: Adding names to the text blockparameters numbers
1192005 SIP_LAYOUT     IMPORT_DATA      Import SPD2 is missing 1 smart metalshape from file
1192204 ALLEGRO_EDITOR EXTRACT          Need ability to extract vias that arelabeled as microvia
6 C9 \3 l2 f  x% _1193063 ALLEGRO_EDITOR MANUFACT         TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
1193418 ALLEGRO_EDITOR GRAPHICS         3D Viewer can`t export image  in both SPB166S015 and SPB165S047
1194305 SIP_LAYOUT     EXPORT_DATA      export package overlay creates file withno package info
1194418 APD            IMPORT_DATA      issue when doFile->import->netlist-in wizard
1195279 F2B            PACKAGERXL       Ptf files are not being read whenpackaging with Cache
1 M: K" y# O) Y3 J6 m3 W5 d) \1195374 ALLEGRO_EDITOR INTERACTIV       Modules are not showing up in Tools >Module reports
1196603 SIP_LAYOUT     EXPORT_DATA      Change form for "Write PackageOverlay..." to better support longer lists of routing layers
6 R3 ?, ^$ M  [9 X3 x6 H; k7 L& a1197302 CONSTRAINT_MGR UI_FORMS         Inconsistancy in selection of objectfor Spacing Constraint Worksheet
1197399 CAPTURE        OTHER            Draw toolbar disappears when usingPrint Preview
1197543 ADW            TDA              TDO does not correctly showdeleted pages
; y6 Z7 B. o' Q, Y+ j1198033 CONCEPT_HDL    CORE             Signals do not get highlightedwhen Show Physical Net Name is option enabled
1198468 ALLEGRO_EDITOR GRAPHICS         3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
) T% {, D3 c& r- {" F% m3 R1198617 CIS            GEN_BOM          Mech parts are showing with Partreference in CIS BOM
1199764 ALLEGRO_EDITOR SHAPE            Allegro crashes when trying todelete small island on POWER layer.
1200232 ALLEGRO_EDITOR INTERACTIV       Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.
1200748 ALLEGRO_EDITOR INTERACTIV       Additional pin edge vertex object tosnap pick
1201056 ALLEGRO_EDITOR DATABASE         Unsupported functionality strip designcreates a .SAV file
1 Z% p. l' ]' a7 d7 \" X  m+ W1201638 CIS            PART_MANAGER     Part retains previous linking inside thesubgroup
1201834 ALLEGRO_EDITOR PLOTTING         Bug: Import Logo command changesresulting imported object
1202406 SIP_LAYOUT     OTHER            enable the dynamic display of componentpin names for co-design dies in Sip Layout
1202431 CONCEPT_HDL    PDF              The publishpdf -variant optionshould have a "no graphics" option
1202717 ALLEGRO_EDITOR DATABASE         About Warning(SPMHA1-108):Illegal linesegment ... end points.
' e9 {1 w! G$ B# Z+ }, a! M1203459 CONSTRAINT_MGR INTERACTIV       Object Report has no mechanism to outputinformation for a specific design.
6 k/ M6 h4 b; ]8 k1204544 F2B            DESIGNVARI       Variant Editor does not warn on save ifno write permissions are on the file
0 K, M& F/ a: }) w0 g9 \6 Y, ~, S1205500 FSP            CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
6 u. n( t- U+ ]5 J* A+ _1205952 ALLEGRO_EDITOR GRAPHICS         Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
1206103 SIP_LAYOUT     IC_IO_EDITING    add port name property to pins, and addSkill access I/O driver cell data
1206546 CAPTURE        ANNOTATE         User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
1206561 ALLEGRO_EDITOR GRAPHICS         Not all mechanical symbols made with Stepfiles are displayed in the 3D View
1207125 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECSet mapping wrong for 2 bit in a 4bit bus
& E" M9 ?7 H: h- W5 W1207386 CAPTURE        GENERATE_PART    Altera pin file not generating the partproperly
1207629 CAPTURE        TCL_INTERFACE    Bug: GetMACAddresses tcl command notworking
1207994 CAPTURE        TCL_INTERFACE    TCL pdf export in 16.6 fills DOT type pinswith black color
1208017 F2B            DESIGNVARI       sch name is not same when updatingSchematic View while backannotating Variant
1 i) o. {5 j& f& ^3 j: ^% g% J: ~1209363 ALLEGRO_EDITOR INTERFACES       When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.
1209769 CONCEPT_HDL    CORE             Top DCF gate information missing
; W. X# G. d7 V5 w1210194 CONCEPT_HDL    CONSTRAINT_MGR   HDL crashes with Edit Via List dialog box
# P9 Z( o% e5 y/ n- M1210442 CONCEPT_HDL    INFRA            Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
1210685 ASI_PI         GUI              User can't edit padstack inPowerDC-lite
$ k$ h& E$ k$ j+ z0 c7 \; Y1210744 SIG_INTEGRITY  SIGWAVE          SigWave: FFT Mode Display unit seemsnot to be correct
1210829 CAPTURE        NETLIST_VERILOG  Shorted port is missing from verilog file
1210850 CONCEPT_HDL    CORE             DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
1211620 ADW            COMPONENT_BROWSE Component BrowserPerformance
5 Q/ O: y: b3 d: G  Z) B1212102 ALLEGRO_EDITOR INTERACTIV       Shape edit boundary adds arc mirrored tothe highlighted preview.
0 ~: B! o' M9 l+ Q0 q1213294 CONCEPT_HDL    SECTION          DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
/ H& s1 M& R: s0 F6 S7 n1213402 APD            DATABASE         The old "ix 0 0" fix  is now causing the features to lose netsentirely.
9 J9 Z) l2 ^7 i1 V1 K- q9 H1213694 ALLEGRO_EDITOR PARTITION        Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition
  K$ X8 D/ H( r% X& E! [1214247 CONSTRAINT_MGR UI_FORMS         Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
1214320 SIG_INTEGRITY  SIGNOISE         signoise command with -L and -k option
1214433 CONCEPT_HDL    CORE             Genview does not update sym_1 withports added to the schematic
) |, `+ E  l" U* C0 ~1214909 ALLEGRO_EDITOR NC               NC Drill Legend show extra rowsfor drills
1214916 SIP_LAYOUT     OTHER            package design integrity check forvia-pin alignment with fix enabled hangs
1215954 SIG_INTEGRITY  SIMULATION       Cycle.msm does not exist error whensimulating extracted net
1216328 CAPTURE        STABILITY        Capture crash
3 }; h$ j8 h4 z+ G& t1216993 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro crash on SPB16.50.049
2 K; g; l1 ~+ e8 W0 c" J1217450 F2B            BOM              ERROR 233: Output file path doesnot exist
1217612 ALLEGRO_EDITOR INTERACTIV       Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37
# b- X& B7 ?7 m: K' ?2 @1217823 ALLEGRO_EDITOR INTERACTIV       Compose shape fails with SPMHIS-473
1217887 ALLEGRO_EDITOR INTERFACES       An undo option to be made available inthe STEP Package Mapping window
1218665 ALLEGRO_EDITOR INTERFACES       In step viewer, the bottom side partsare placed above the pcb board surface
1219053 PSPICE         PROBE            PSpice crash with the attachedDesign
+ p. \* y# b7 c$ ]* b! A1219067 ALLEGRO_EDITOR EDIT_ETCH        dynamic fillets behavior is unstable
1219095 ALLEGRO_EDITOR MANUFACT         Design Cross section chart is taperedfor two layer board
1219126 ALLEGRO_EDITOR SKILL            Skill issue with axlRefreshSymbol()
4 T9 o! H: |- r2 k, Z1220701 ALLEGRO_EDITOR INTERACTIV       View > Windows > Worldview(showhide view command) fails with command not found
4 ^* K# \+ i7 Y2 s& b1221057 ALLEGRO_EDITOR REPORTS          Units in Cross section report forspacing is not synced with the design
- H$ f+ a" B; f7 |! e1221139 ALLEGRO_EDITOR EDIT_ETCH        Delay tune is not tuning differentialpair
. s' n- a! e% O* J2 W1221157 SIP_LAYOUT     IMPORT_DATA      import spd2/na2 file is not importingdata correctly into sip
1221163 SIG_INTEGRITY  GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
5 l4 c% H% D6 }7 ~% X" ~1221416 ALLEGRO_EDITOR DATABASE         strip design for function type
. H$ _6 e& w1 ?9 X# ]7 `" J, w! j1221931 ALLEGRO_EDITOR DATABASE         Fatal software error when embeddingcomponent
1222105 CONCEPT_HDL    CORE             Moving Pins around the edge of aBlock causes the text of the pin to change its text size.
) f4 W- b- y+ ~; Y' `1 w, e0 W% {1222124 APD            DATABASE         Same Net DRC's exhibiting inconsistentbehavior.
8 K8 t+ b, M! u( |$ g) |; U$ K9 f1222272 SIG_EXPLORER   EXTRACTTOP       Cannot extract net or open SigXplorerafter selecting a netgroup
, Y+ r" b+ f/ \1 O6 v1222329 ALLEGRO_EDITOR SHAPE            STEP-Model  Symbol which has place bound bottom is on Top
# ?, Q! R; M, C' v4 {/ `1223183 SIP_LAYOUT     BGA_GENERATOR    Getting an incorrect error message whenusing the BGA generator with a long BGA name.
1223662 ALLEGRO_EDITOR REFRESH          Allegro crashes when trying torefresh symbol
1223932 CONCEPT_HDL    CORE             DEHDL block desend does not find1st page if its not page1
0 S/ t$ l' [3 B6 K+ A' B0 h3 _+ D1223940 CONSTRAINT_MGR UI_FORMS         Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.
& d8 r' P, `* G+ g6 c+ S1224127 SIG_INTEGRITY  IRDROP           Is the old static IRDrop in 16.6officially supported?
1225492 PCB_LIBRARIAN  CORE             PDV expand vector pins resizessymbol outline to maximum height again
; `6 o8 V0 e) N1225546 CONSTRAINT_MGR ECS_APPLY        nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
1226405 ALLEGRO_EDITOR INTERFACES       File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
2 u/ Z7 O  G" v* B7 t$ C! @1226448 PDN_ANALYSIS   PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
$ L0 \4 g& P& v9 F0 C$ @$ p1228721 SIP_LAYOUT     OTHER            File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer