Cadence SPB OrCAD 16.60.016 Hotfix

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Cadence SPB OrCAD 16.60.016 Hotfix | 853 mb
( R/ O* b3 u, g% V8 Z. { DATE: 09-27-2013   HOTFIX VERSION: 016

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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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( I, G( k9 c9 r548538  CAPTURE        NETLIST_ALLEGRO  Enhancement:Include mechanical parts in Allegro netlist

+ k0 ~+ {4 x$ n) O0 A: D5 r% b, J- Y1076579 CAPTURE        GENERAL          Display value only if value exists
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1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.
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1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled

+ g/ O9 ]5 n( u+ V! {3 A  G3 F1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
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7 s3 ?6 \' o7 H6 G' \# p1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape

1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms
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1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

+ b2 f9 J4 p6 N8 U1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor
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1 L' i4 C. y2 q1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.
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$ p1 U8 @, O4 o* A' `1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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" z" E+ w! c4 M$ I1125611 CONCEPT_HDL    OTHER            display unconnected pin in schematic pdf.
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1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.

. w2 q0 @6 H. Q3 b1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.

1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set

1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.
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" t; v5 S$ F+ b; ~5 R, \1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
# X* z5 S. o# q) }1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells
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; \4 U- p1 Z! c1142949 CONCEPT_HDL    SKILL            Usage of "Preferences > License Settings?in FSP
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1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract

1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate

2 h7 e/ m% J) [. s1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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! i0 L5 ^+ \+ J$ D1145286 CONCEPT_HDL    CORE             Directive required for switching off the console

# i3 G' ?1 ]! U# t8 m1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.

1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net
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1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.

/ B7 n* j; U; R, x5 c. V  B1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
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& J: }6 R& A7 B' \# h3 Q1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg
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* m+ I" I- Y) o0 ]8 |3 H9 x1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname

1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export
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1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.

+ ^: @3 P; h2 f6 g4 z1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form
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1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.

  `* s& |8 r( p% z) o. c' k# C1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed
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1 {5 X8 ^+ C  w, Y1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?

1156858 ALLEGRO_EDITOR PADS_IN          PADS Translator: Missing drill on square PTH padstack
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1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.

1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation
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  f0 u8 y! T- p7 z/ p1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out

/ k+ {5 r. p% y4 m1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle

. h% F8 K0 L* @$ {- ^1 i- P1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.
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7 t0 u% @* n3 v& R8 e6 J% E* b4 S1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file
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1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.
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1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template

1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file

1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation
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1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines

( e! {  ?8 D2 T1 t, s# Y1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS
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1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape
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1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output
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" \/ |% M# f  P" f( R1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.

1162562 CAPTURE        STABILITY        Capture crash on second attempt of pspice netlist creation in 16.6

1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly
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4 z: s$ U& _: e  Q7 I1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE

1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database

1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.
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6 d. h* L7 H! O1 N4 i3 d" z( K1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace

2 Q( C7 f) U9 A2 R( [1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin

1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
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5 m3 A9 t$ c, }1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list
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1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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6 _% g: ^' }9 [( [/ N1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.

1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.
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1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs

$ W. ?+ N) `% H; U! D( p% k1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window

- }" I1 d8 s* a, w  t4 b8 o1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)

1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked

) D) D# \: _% b! r. K$ z1 h1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias
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0 M2 l! s, k( y9 X1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle

1166074 GRE            CORE             GRE crashes during planning phases
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1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed

) f! I1 ^" s, z5 L/ j- \1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move
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1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move
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1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue
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* P8 m4 J# X; r1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
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1167887 F2B            OTHER            Improve message on symbol to schematic generation
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- E/ G* C5 ^/ o1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.
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  y) s( x) J! w* f1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.

. @. d7 H3 g2 S5 a2 L3 e0 l" d1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk

3 V5 v& Z3 o7 v1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check
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4 H( A; U3 K$ q8 h5 {1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty

3 F$ K/ C( U4 G1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts
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+ P; Z8 R5 d8 t: B. P1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts
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% ^5 g! U4 X% S1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule

1 T3 \! G2 Y( a! |1 S+ `1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file

1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.

1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components

1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing

$ D9 b7 q, H4 Z2 t7 u2 J1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
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1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.

  G; ^3 [4 p1 t7 g5 b1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads
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7 H) N8 n* P, w! n7 O) L- F1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm

+ O0 O: S/ c, J  t8 e2 ?3 R1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific
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# b7 V4 N* ~0 }+ Z1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically

1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules

1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
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) D; c$ H3 [" f' Z" \$ U1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl

, W1 e* X; J3 Z! t8 T& b% n1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.

1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height
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1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer
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1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.
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1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.

: l: P9 e; D4 `9 s1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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( s* ?, \. I; u1 I* u4 M+ ]" Y1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.

1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
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1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing
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1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin

5 |6 s1 `. }. o5 P/ ^. g1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
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- y/ w+ L% p- R( h8 }: A3 M* h- Y( q1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box

* P& M- |" }" x. Q, B1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".

8 `; b+ q1 w) n! ]2 z1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!

" M2 V; G- ^* }- d- ]6 T. }1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up
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1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash
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1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA

1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block

1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs
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, y$ C+ r" T$ T0 U) q1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks

% q' ?0 o+ ]0 g) _6 c! x1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.

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Cadence SPB OrCAD 16.60.016 Hotfix

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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466