Cadence Hotfix_SPB16.5.044-2013-6-7

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Cadence SPB 16.5下载地址（Hotfix更新至044）

Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
http://dl.vmall.com/c0sfvdb4yy
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Hotfix中只需要安装最新的版本即可。
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DATE: 06-7-2013    HOTFIX VERSION: 044
/ {0 _1 P) F- ^===================================================================================================================================
, Z+ F) v' S7 _. s8 NCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
. @. V1 u6 ^* @. s& S+ M1 e  x1055338 SIP_LAYOUT     DRC_CONSTRAINTS  Soldermask to Via drcs on bondfingers
1084716 ALLEGRO_EDITOR OTHER            Getting an MPS error when updating CM from SigXplorer
$ _( @3 J3 s  |9 H* Q4 q# }$ k1104145 ALLEGRO_EDITOR SCHEM_FTB        User defined properties do not appear in PCB
1106116 FLOWS          PROJMGR          view_pcb setting change was cleared by switching Flows in projmgr.
5 m" @: Z8 _3 z: R) L) a. u1106900 CONCEPT_HDL    COMP_BROWSER     Component Browser performance utility should honor CPM directives for include and exclude PPT
1110323 APD            DXF_IF           DXF out is offsetting square discrete pads.
1119007 CONCEPT_HDL    CORE             PDF Publish of schematic creates extremely large PDF files
1121020 FSP            MODEL_EDITOR     Cut-Paste from Excel causes empty cell in Rule Editor
# F# Y2 G2 ]$ W* V1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change after saving and reopening.
8 `$ h4 c$ n* e1122781 CONCEPT_HDL    CORE             cfg_package is generated for component cell automatically
( i' I' ^0 p$ I& Z. X1122909 CONCEPT_HDL    CORE             changing version replicates data of first TOC on 2nd one
! I) F0 m1 t8 I0 p5 V) y( y1123581 ALLEGRO_EDITOR MANUFACT         Dimension Line gets changed on board
1124544 CONCEPT_HDL    CORE             About Search History of find with SPB16.5
& x* j6 p+ O# `2 A1125366 CONCEPT_HDL    CORE             DE-HDL craches during Import Physical if CM is open on Linux
1125628 CONCEPT_HDL    CORE             Crash on doing save hierarchy
1126182 ALLEGRO_EDITOR DRC_CONSTR       Shape fillet DRC in same net thru via to thru via was removed after update DRC.
& \4 e) C0 Z5 Y9 U3 K1130945 SCM            SCHGEN           SCM Export Schematic does not copy all cells in the library
* q8 `9 H7 V2 n2 o* q1131567 CONCEPT_HDL    OTHER            Lower case values for VHDL_MODE make genview use pin location to determen direction.
1131650 ALLEGRO_EDITOR PLOTTING         PDF Publisher doesnot display few component defination properties in Property parameters
1131868 CONCEPT_HDL    CONSTRAINT_MGR   Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1132457 CONCEPT_HDL    CORE             The schematic never fully invokes and has connectivity errors.
1132575 CONCEPT_HDL    CORE             2 pin_name were displayed and overlapped by spin command.
1132638 ALLEGRO_EDITOR DFA              'dfa_update' crashes when running the utility on the attached foder.
1133677 CONCEPT_HDL    CORE             Cant delete nor reset LOCATION prop in context of top
* M, I( R! ^6 G* R9 i* Z1133791 CONCEPT_HDL    CORE             Cant do text justification on a single selected NOTE in Windows mode.
. h& P& V7 m3 F, w" j5 t6 i9 Z# ?1134083 CONCEPT_HDL    OTHER            Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
1134761 CONCEPT_HDL    CORE             Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
1138586 ADW            MIGRATION        design migration does not create complete ptf file for hierarchical designs
$ R, i, ^. y4 m- X% d) V. N1139376 CONCEPT_HDL    CORE             setting wire color to default creates new wire with higher thickness
1141300 CONCEPT_HDL    CORE             DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
1142876 ALLEGRO_EDITOR SHAPE            No DRC error when airgap between place bounds exactly zero
' h# F/ _& p) T* s1142884 ALLEGRO_EDITOR OTHER            Boolean type user defined property doesn't export to the PDF
1145112 CONCEPT_HDL    CORE             Warning message: Connectivity MIGHT have changed
7 @$ e/ `, B7 @' s* V6 V6 [1145235 CONCEPT_HDL    CONSTRAINT_MGR   DEHDL CM gives error when trying to launch SigXP
1145253 CONCEPT_HDL    CORE             Component Browser adds properties in upper case
  q  ?; F- p& R1145284 CONCEPT_HDL    CORE             Publish PDF crashes DE HDL
1145333 ALLEGRO_EDITOR SHAPE            SHAPE boundary may not cross itself.    Error cannot be fixed.
% a0 `9 O5 D1 I' ]3 c. R1145856 ALLEGRO_EDITOR DRC_CONSTR       DRC Line to Thru Pin appear while Fillet be added
& P8 q2 U  X& U3 D1146287 PCB_LIBRARIAN  CORE             PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
: u: p, s* W5 z' o+ A/ r" x. {" ?1146728 F2B            PACKAGERXL       DCF with upper and lower case values on parts causes pxl to fail
1147326 CONCEPT_HDL    CORE             HDL crashes when trying to reimport a block

linsky2000

谢谢楼主分享！

iepdcay

可以下载 ，谢谢分享

ckcpyongfu

这种更新的补丁，是怎么安装呢？

linsky2000

ckcpyongfu 发表于 2013-7-31 17:30
这种更新的补丁，是怎么安装呢？

2 I3 a& `. j) m0 I9 ~# {https://www.eda365.com/forum.php?mod=viewthread&tid=76626
这里有版主介绍的安装方法

fxxxysh

能用吗

joanna413huang

看不到

gaobj

看不到

h3jt

能用吗