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DATE: 05-24-2013 HOTFIX VERSION: 010. I$ y$ H, C* D. L2 w1 [1 k4 X
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
( `2 U0 S( Z. @! Y===================================================================================================================================
1 `- j& y6 ^' ]: s6 E1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer9 V: x J! M0 I" C( ^2 P3 `
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
( X" d/ W1 w; e; n) R1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
$ n b8 B3 S- n2 b+ k" q$ }1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
8 p% p& q/ q9 `& j3 b1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6& L/ U$ Y6 ]' U! I5 W
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
! u: M$ a# p$ |7 j9 c1 e- M4 w- Z1131775 ADW LRM LRM error with local libs & TDA
* {9 p3 a5 ]8 M D S1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4& X& N1 x; T: u
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo) @6 ~* f, u1 D6 i0 |, L1 n& Z
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
5 s% t/ H) l* _6 L! D$ V! i1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
, R# H6 c. @9 R) ?/ y) Q. X# a1 F, m1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?7 j$ j. K' p$ Q& f) ~
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
1 k! x9 u7 z: _1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor" Y; W, ~# O: |: E6 i7 ?( x
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro9 K+ [0 g0 O$ u7 o1 l5 T R$ p$ [2 M
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
! w/ H+ e( x/ {0 ~! T+ L7 O+ R1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.) X0 g5 i+ v _6 T, c, r! ^7 `* i, K
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash% N5 f) J6 t! \* {' T+ ?- p+ ]( j8 p
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF4 E% {! \, F+ D! u9 w( q
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
4 D& [) z; a' W/ W) I( S* H y; B) t1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
+ C1 [! v! E9 k1 p7 `
& t* ?/ n6 _" ?0 X" YDATE: 05-9-2013 HOTFIX VERSION: 009, I, Y4 p: p$ P2 Z$ K. g [6 w& ]* k
===================================================================================================================================
7 v8 O! S0 B: E1 d3 tCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ |" _. Q: X$ C8 M" I" }$ ? |$ z===================================================================================================================================
' w* m: ^1 P- C7 \1 M( c0 R: X961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp) l/ h: Q+ _" A. w) m: g
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function2 @: ^9 w/ B. R2 L
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da5 ^6 G+ H1 h! y
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB( }8 ~, B- u: A6 F+ R7 }
1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
# G& U8 D7 L, U% o4 m& P1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock, Q4 i" p: U7 p: m3 Z$ I4 A
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
- w0 e: N- {" G5 T8 }0 w( Z' Q1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro) V/ b# J: _' t( G- ?: o
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
0 I) p4 ~( t B" o+ \$ w) `, r1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl" m( `$ H( Y5 r6 M5 s, [
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.' e# g& ?+ a. K `# g. H) ]7 j
1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
/ W( h5 ]. k7 m `( T$ U5 R1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent5 r- Z5 S3 T5 h" b( [1 V* O
1126096 SCM REPORTS Two nets missing in report( q6 x# z. p; j9 A- s" [- U+ P
1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD9 ?& g& [1 w* c
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
* \% O8 i1 S) W# @2 d, g8 d1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
9 q+ \# n; s0 u, L7 j0 J/ Z6 U8 l! J1130737 F2B PACKAGERXL Error - pxl.exe has stopped working8 W$ @0 w. ^) c- T
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
. W3 P8 C# ^$ R- Q4 t) H4 R% g1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.
8 ^4 Z% }" ~2 ?. m1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.9 ^: ^0 H' U2 t9 I8 a5 U0 f
1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes0 I# b$ H% C3 W9 O, b
1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes+ _2 W' L8 S( P, D* d
* C) s, x T9 f! P, D; L
DATE: 04-26-2013 HOTFIX VERSION: 008
$ q1 M3 U! J0 I! Q+ G6 H===================================================================================================================================
& n$ {+ g& i2 C; {, {8 Z5 NCCRID PRODUCT PRODUCTLEVEL2 TITLE
, X J9 v9 U8 s. H===================================================================================================================================! f. f3 A3 A, @7 g& G W2 o
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit. J7 B% R' z5 }
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
6 S6 j' q( E' L& y1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device3 \& }% J! l7 O4 \; U, P1 a u
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
( G) M% ?7 b2 q" `8 P. _1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section! \ V3 O. |; \: S& M9 ?- W
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running: @$ A' A0 U$ g4 g
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color./ I, r1 J3 K; o, z5 b' D+ y
1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence/ K8 s1 }* g0 s5 | |( l
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.. H" v0 u! G* M# K# G
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason9 ]1 q: a+ b9 D/ b$ N+ {0 `
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.: Q" o; ^3 _% o9 U0 c% j, y
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered? m/ a2 o- r( \1 V' e
1120414 ADW LRM TDO Cache design issue! Z0 Z# F/ X) }1 x% N4 ~7 W
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
! ~( @7 O: R& F/ A$ w1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups; F7 C' }0 W: l3 m" M1 g
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
" z; M; C0 T3 L1 H6 W1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.; F, w& Q: M. |* A- E9 o" N( N
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
( [8 i- C. h! w; q) z1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.% c" J* o8 M/ y" Y9 m
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable% {5 v+ D' t+ A0 ? z0 O
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file8 G; T T( P. I+ d, w2 J3 w% h% T0 \
1123816 CAPTURE PART_EDITOR Movement of pin in part editor$ G4 w6 r ?+ J' P
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50) z" z* b$ K7 S# }) B& P# D/ }
( u2 \ b2 M9 ]DATE: 04-13-2013 HOTFIX VERSION: 0076 O3 P1 Q# n: E( z) _3 F
===================================================================================================================================. a5 G9 k0 L: h Y! \, V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 H; I k: J7 P3 ~9 V2 \+ |===================================================================================================================================3 R* j: u: v$ P4 l
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
$ Y( X' n+ j" m3 z3 F+ ?1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
# U& C; T& O! X I1 o1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
0 X3 C2 c( X& i7 _; g1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components, g. S& [ E) ?9 C0 N( u
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly8 \' L: J# w, A
1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
3 j; Y& W3 y Y$ @1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.3 W; v9 V T0 m+ t* r! T1 J
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
0 G' s' z% ? L9 i* _) e3 S$ [1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear, {2 x2 L1 T. N1 i/ y. y
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks; S' c9 @' `8 ^# K) W0 ]: J, f- M( a
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?* { I) d+ k% r! f
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh' z1 Z2 C: x$ U$ h2 e$ O1 T
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh, z/ Y/ i) s+ s8 y8 |* [# ~
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
/ f0 e! z. W) m, V. I1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
' h: P/ e7 Y* [1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
3 o/ z* K7 a: S% o6 f2 p# H+ c2 b1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps6 H4 k2 i1 V& { U0 |
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
( M5 B0 o1 l2 L+ J1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.* d$ w9 X! S. p5 d; G% c. U
0 }- ~. @% L8 n) a4 k# A( j( d U) |
DATE: 03-29-2013 HOTFIX VERSION: 006
8 I; Z4 |6 L C- {1 C===================================================================================================================================
' V% k: f) T) v. D, _7 ^CCRID PRODUCT PRODUCTLEVEL2 TITLE4 l9 B1 P, d4 s0 U
===================================================================================================================================
# T" D# |: ^1 n& M# J5 P625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.. A( U2 m( v+ D( H9 l6 ^
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
3 ]3 c2 i" }; \8 I9 {650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".% _8 t ~) ^% _4 S% J
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
7 V$ a+ i: g7 N687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
; d5 y# F5 D2 S C( r, f787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics) j* e7 S, y/ B, K2 c* w1 ~
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
0 N5 M3 r5 p' O L$ D1 r1 N834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
: D8 M1 M, w; [835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.2 ~+ u% d1 X$ y' l2 P2 ]' O* N$ ^$ I
868981 SCM SETUP SCM responds slow when trying to browse signal integrity" \+ l7 f& x# _/ _& }8 P3 b3 {
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
; `: l% E3 I: b' ]% @$ x' n873917 CONCEPT_HDL CORE Markers dialog is not refreshed# Y+ `- J0 f& n1 U- j
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
7 q6 g5 b- g7 W7 a! p888290 APD DIE_GENERATOR Die Generation Improvement
6 d9 [ m P* m- _$ u( g892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
) W, @; g" i0 W902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice$ n4 L; ^( c. ?; |9 b: S9 ^% Y& D8 g
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
4 a: d2 |( g) ]4 e$ m' P9 X922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols3 L y' f5 s1 s
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences% t7 u# ]; q) ?
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC' t! W/ p/ ^+ ~
945393 FSP OTHER group contigous pin support enhancement
/ U* y" }: x/ m* ]) b969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database* q! z9 M& ~; s+ z9 [- U6 O
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes8 y& M1 \4 @ g4 C, V6 Q" y) y* V
1005812 F2B BOM bomhdl fails on bigger SCM Projects
7 s# a; y; Q, g9 v5 [; p& S* ] r i1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
$ A4 {, Z* I/ z) C& [$ u' p1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
. s" q) {8 P* \( b; Z1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
) b: q2 K+ w: K3 m( O! E. D* G1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
; M6 B6 M# _4 E: s# d7 a8 M1032387 FSP OTHER Pointer to set Mapping file for project based library., m& a& H. Z' Z! ^6 H
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 燕LL PLL_3 does not exist in device instance�- w: _# [2 K9 C _
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
8 c f' b1 T8 U1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
8 i* M( ]+ ?- ^- r1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.# p5 h; f( f( J' i3 \3 x
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type9 `/ l! c$ g4 X& w! p
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
- w# r! Y- L0 x7 x% Z% d" }1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation3 P9 y* w$ y) a# }1 o7 c
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects- W2 x3 N5 g {: y# d8 U- g
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
! a$ z3 k' }0 ~1 A/ C1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
+ S2 ]/ p4 s$ p. k1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs9 B' G3 M/ {3 [0 F0 ~
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
/ }% M5 c' o' Y9 k6 ~7 K9 o2 V1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings+ y b0 N! Y- m- c) B) w* N# D4 E$ I
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary* a$ j% v" ~. S# g' L
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
, S( J8 u6 A, g1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
5 l( J2 I0 l' N) M+ Y( h6 F$ G1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
+ g, S# Z" x$ L1 z. z3 A# ]5 o1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 454 o6 r$ Z3 Y0 t" L9 s9 ~( ~5 \) V( G
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
' f% w f& W0 \. E. w4 n. [* h1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
" |$ u. F+ c$ e7 A" L1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.3 l3 q2 R+ h# U8 K: o* X
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)/ s2 i, k6 R6 _# D; R0 h
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
3 X0 h3 d7 p: f$ D1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
, A) {& e ?8 O. X9 N. I1 S1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
1 i# L6 Q/ h8 @( T( g2 g9 n* `. x1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects% [- B$ t" S% W- [. ?5 a8 N, n; h
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format+ l; _4 k( h" ?
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net" ^; C0 t, u3 O4 }( i
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
1 ]" q- j r) M" a( k( s1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
$ a5 _& [/ E+ [3 j! h1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
6 K- N6 D6 ]5 [1 E# J' i3 E7 |1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.$ S* I7 x# E: {5 J" t" A( W+ {. \
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors, s5 j4 C g. K6 l
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
* o9 j6 T7 o# T8 |: B1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition& T- L% d& N9 F* e- x) [$ F7 E5 `
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
) F* m) k. _; E1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
! Q# u5 U/ W) m1 @" N1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
+ P- R1 |* B6 Q! R* O1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.' _- h4 ~9 V4 q
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
$ x2 h7 v4 Z2 Q* d- N: z1 R1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3) U+ f2 H( q; U: _ S( M8 J. r
1078270 SCM UI Physical net is not unique or not valid7 Z$ x- \% A5 G
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted: Y1 m5 ~" H5 _, R
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle0 S% Q% i, S( s
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
* d2 J9 J4 ?6 a( X7 y1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
6 b2 N- U# N+ i4 v1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
9 m: q4 W- c- `- ^& d3 H1080336 CONCEPT_HDL CORE Backannotation error message ehnancement/ G+ @* O0 @1 C& h& I6 f" ^
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
/ s, v, D! A3 O- g$ _. i1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
# [5 z! O% q/ M1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error3 k$ k1 o' C% U4 R8 R6 s
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.1 h" X% j& C8 j
1081760 FSP CONFIG_SETTINGS Content of 澹PGA Input/Output Onchip termination� columns resets after update csv command
6 ^; H! R8 u7 @, c& e$ y6 ~1082220 FLOWS OTHER Error SPCOCV-353
, B- S- Y" w- o- y9 q1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
( s3 a9 v& h9 X8 ? S1 g. Z4 U1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
5 p# _: }1 ?3 p8 h6 o2 o1082737 CAPTURE GENERAL The 澤rea select� icon shows wrong icon in Capture canvas.
1 A9 H/ R- o) [0 C/ p' M; a1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name/ F4 U5 l9 _. v3 m
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
& x9 |7 x* K) [& Z" i" S1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher/ w' X% q: e" ^9 y. w/ u. c: e
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
- K4 l- ?5 G( n- s! [2 `$ C1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
4 b2 ?- q5 e* l) @, I4 b1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
% ?# l5 e1 q7 G9 v u1 {1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
4 H9 Z/ ~% k! ^, C _1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters- u' v* ^: ]: y4 z1 [
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
3 I4 V: z* j7 K6 o1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results: A8 x/ g) s6 k! L! e
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file., m1 C; O5 ^$ [: `; b: e- P% A
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
3 v1 A( E, w& A! ]& h1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
3 d: B0 t# Y5 W1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
+ \) R) V" }! g9 N' s1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
- m* {5 I5 g4 ~& m& x1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design4 ?# q, {0 U* p% a8 J# P
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated, q0 m0 d# n' }' S, q+ ] ]: k
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins- ~& z* t& N2 e& A/ W
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
9 K1 ~4 M8 ^: j1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.3 t+ \4 q& a+ j( S4 G
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.1 E% p. U6 {: m
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
% v: w* b Y( D4 D- k) j `! g% t' s. [1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
' d* \& }- j+ h9 E4 g0 ~; P1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice5 c3 h/ H0 G& ~, J) a/ a
1088231 F2B PACKAGERXL Design fails to package in 16.5
5 C; W4 O" n8 k2 p1 B: A1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
, ~) K; m( [6 }8 {) s1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor/ C; z. k% E# N: ^! R2 q
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager- M1 M' d; W: q: S0 p) z. G( c
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?& M2 F3 _7 f& S
1089259 SCM IMPORTS Cannot import block into ASA design
" Z# L2 w* B% E2 y. d( Z; W) b* A1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form& S; W) {( M1 v7 I" u8 {+ {2 t9 x. }
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
4 w/ Y# b" w9 q! X1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
4 ?5 ?% p- _1 o+ `% I1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
! p0 \* a* s2 a2 r- q+ I1 o0 C: e1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
; n R# ^7 r6 V' B% ?) V1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.# }0 Y6 z# z: _3 a3 w
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-228 p3 r% I. G' [8 {) j: v' o2 b' t; e
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
7 B* J5 a2 Y" u X! n1 C- M1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
" p/ h0 H' b. T, G9 U8 m/ V1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled" g6 I9 r) L U: V4 @0 \
1091359 CAPTURE GENERAL Toolbar Customization missing description
5 K! J- Y+ V% f* ^5 [/ @1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive: P9 q5 [; B7 h5 V2 H
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time) o t' W! i) F
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5$ h& r/ N1 j! W% k5 o9 p
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design: p) C: G& h2 n2 @# x- m; n9 w
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
% n* ^2 N W9 F+ f% X/ j1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters% K" I! a' [# M( U- t5 z! D
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error; q; V8 C p# p Q; S* [. @4 ]
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder7 o8 b- a7 e% ?8 R( y- Q" @; \
1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor9 F4 _. m" _7 o* \% C, w5 Y: S
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
0 n* |% c7 q/ I/ J, R7 }1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
+ a, \) _2 f8 o. _$ ?& ~1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.4 ~1 E7 I2 S h9 h
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?6 B+ p) m$ e- ^$ c# K+ B
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic7 k5 [: |0 f# j8 s% ?
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
+ d m7 W7 C) D' K8 H6 J5 G- g1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet, e* r/ i9 o+ o& l
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
0 j* h. l& F& l& c& X6 N+ {; F1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
0 Y2 t: f# m6 s" j0 A1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
* l: H# C) z# k1095861 F2B BOM Using Upper-case Input produces incorrect BOM results. Q2 b, U% C) d8 m8 A; q! X3 w
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import' A0 U8 H/ M% V9 t
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
9 {& h- h- X: w5 n8 L* |1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias0 R1 a% v6 ?% ]0 j
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate: s/ p8 v6 [' Y
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
: A* x6 _3 w% @9 K# v1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL* h; N. q$ ]( Y' d/ `* W
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
% U! v2 y0 H0 [7 ?- G( E" L1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side3 D9 U [6 ? r+ J% B8 b) Z; J
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
6 h0 X- Y! p( h* W x$ t3 W1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
6 S0 n+ ~5 [5 }1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives6 g( f( j; g+ |% X/ R- H( R/ x: {
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork0 r4 X4 }" F$ P5 t1 ?; w: G4 K0 B- h
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts$ h9 W' G) o" _* }+ g
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
1 U$ S3 i0 t, p$ E; A8 a1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
5 r' X9 g) X/ d7 T3 _% V1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties: ? L% d5 h8 S$ \. d5 Y
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
$ j# a7 g' C# H6 ?$ w1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
& y: G* w; ^* X( [( {/ e* d1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
- I: |, v- w4 v1 J( E3 x7 H( N1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad) K& O f. l$ H$ Y/ N4 `; ]6 L" s
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
9 K8 t) U4 B$ W+ P: M) ?! ^0 ~1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
" u) G: e& {3 g% E" S r1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.60 z: p4 O- z% w0 ]8 |
1104121 PSPICE AA_OPT 燕arameter Selection� window not showing all the components : on WinXP
* F4 H, c! |5 c% o& D9 o1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly6 G% t( u+ f: W" l- A( {" r p
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
- v v `( M* [5 Q* h2 @& _/ q1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
! {: |+ A; Y p1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.1 ?$ M- }) C! B7 i+ b$ s
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form) m s6 {6 _7 N, E
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
3 A7 V, P# u" V6 o" N1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked0 d D) O; P; _8 s; J: w
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax2 l0 |3 A8 b+ y% F4 r+ V A
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
* j% J9 ^) ?7 S4 w& {, \; |: _1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only) {2 Z/ ?. P) m+ d$ l; M
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid6 Y) M. H# Y9 L' Y+ T# F$ s
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
' c+ n5 E2 b7 I& ~2 T* G3 O* N5 Y1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
+ f* B1 _! b. Y; |1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
6 O( y# d$ Z9 u2 g7 y, r1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).# v9 \2 c, S+ C5 W, ]% ?; O. W
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
* y) p; ?" J" h; [/ C/ j$ g4 h1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
8 O+ x- I4 L& @* z1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
3 j2 {$ @5 b% q- s+ i8 m1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs! B( r" m5 f" W& }3 G! o! u
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
" U" G9 u: O; H7 P5 k+ f1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
: e7 i6 _" q/ w1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON& W; N+ O; y% c9 |* l
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
?% Q$ X/ r0 C2 U. V/ j1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset8 C ^* a8 K/ o$ A* {6 _
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters: h) ^ x6 a/ ~! {0 d3 d
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend: i3 m, n9 ]" a g1 \" H2 K1 q
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
/ i& [6 t' R$ `- H3 F! P* }1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint5 J0 ^ `" n9 F/ g
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
" m$ V. M+ K& i% o/ X! m1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
; g. H& k. s, S {* z% d9 K& Y$ ?1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
6 h8 `+ C& o7 F4 B) i( _6 H: ~, t1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
6 h3 f U) {7 F, c2 e( a4 d6 l
$ t% j& F+ ^6 n0 U# f3 D3 E/ m) {DATE: 03-7-2013 HOTFIX VERSION: 0057 v+ T$ ~7 T# P6 P9 I7 k- h
===================================================================================================================================
6 ^- z5 L+ \! _5 y; a. F* h' e$ N! [CCRID PRODUCT PRODUCTLEVEL2 TITLE) b! g8 z9 N5 b( y" F" X
===================================================================================================================================1 q5 q2 ?7 r' B E( K
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102/ s) S' C2 i' d. f
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed% k8 r( @. u9 X+ L* G' x/ e. i1 j
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently6 ]4 T5 V- x0 q. m; @8 H6 `$ ?' F
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
D* [! s7 z: W0 x% e) G* d1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
! g& r1 f M+ [( j1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed8 y+ ?' \9 j1 }2 O" [
1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
! z7 Q$ h+ d! K0 Q4 y8 l- W1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6$ | A4 Z" E0 i3 w9 u7 X- O
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.( |- f3 ^- f4 w/ j& J- J. Q
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design8 A h w4 ^" q' [- s! \- b2 j* ~
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional; Q( s ?* ^, j$ [
( \) n7 }9 G5 H/ }1 R
DATE: 02-22-2013 HOTFIX VERSION: 004% d4 G$ r- w! b" q
===================================================================================================================================
3 {& Z3 m( ], d/ r) yCCRID PRODUCT PRODUCTLEVEL2 TITLE0 v+ _1 U* _7 J# ?
===================================================================================================================================
% b2 u# p/ q" \* Z6 f1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly. G, `4 p% e5 E, b% B2 E& O
1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing
" C/ X ]2 j' s: @9 h1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
) y7 s- h6 j P2 A! M1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
# w; q7 Y1 l& N% N. t5 z1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend0 h2 o3 t, P* l) n z6 O. m
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report
' p7 X" |) S. N2 w) N1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command- w/ _. h, Y. I' r
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
; [; L1 c6 I; S h: w1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat
8 r' p" `7 T' u: ^1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.2 [ ?: ~2 ~! M# y% k" P
5 n* z/ H- l% }5 d" n8 H6 ]
DATE: 02-8-2013 HOTFIX VERSION: 003
. t8 Y W1 l; V' Q9 Y. ]# A) ^===================================================================================================================================
$ P- u* P- T0 K d1 DCCRID PRODUCT PRODUCTLEVEL2 TITLE8 b- r9 L! v |/ i# K+ w* b" @1 e
===================================================================================================================================7 ^" m, G V2 Q* X2 L* _) Q
1077728 APD EXTRACT Extracta.exe generate the incorrect result
7 V: q. v8 m2 u- i. X1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF
U K3 S' `* D* r, J4 C1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer/ r3 Y! u& R8 S$ Y+ t/ r1 v/ n
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.$ ]; ]8 U j/ U h9 V3 ~
1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on
1 R+ D; X, i3 k1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent7 R" R9 L) V, A
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
$ `4 s2 @3 o; H& ?1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
1 t6 A) x, {7 {1 v( h& u9 F1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn篙 show up after 燙uppress unconnected pads� option.
3 p+ v, z/ z7 |$ L1 L5 k8 c1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff r7 \3 k1 z5 s, ~( C
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible% M4 Z$ a- K# O) J: a1 d
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
# d; {* Z+ p- B: _+ @! N( l1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component., P0 Z2 {6 b6 e( L' \: B
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.# v. q* l; w1 P4 z4 |3 a! C& |* q1 {) } p
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.. o2 v. f) A! D& o! E E
9 s1 w- {0 o1 B$ {- R% ?
DATE: 1-25-2013 HOTFIX VERSION: 002
# g/ s) Q3 q6 m5 l===================================================================================================================================) j7 a4 e9 N) p7 V1 M' r6 @
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 w# _6 p1 q& S* d9 @8 G; E
===================================================================================================================================
+ W! j5 S" U5 S# \& c# Q491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
3 N( h x& V: [1 y2 I9 r% m" \863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"5 T, ]" ^5 Q, l$ A+ f) O
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes9 J( {+ |2 _! N/ C4 l2 \+ @3 }
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable7 y9 W0 W! F- N( K, T
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
8 v' I" Y( `) @# N W1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence+ V& ~5 B. ^, G3 o- W- i7 ^
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
8 Z1 \' Z+ G* \' E7 X0 f. o1 I4 Q1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
, x2 J: q0 K2 M* ]4 z1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.60 J9 k. o" e5 f5 ^) }$ h% C
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.2 q% ~1 c2 |: S4 F4 {
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.3 J5 _0 Q. Y5 `. e, S' b: K
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
& G8 l& J# t2 O. M1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
; r2 d: G9 j+ z& S& b P1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white4 g7 I2 E. W9 P. j# \
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure2 \7 D4 B, K! `( r( i7 a
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer/ d& i- r* i: T
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
2 B- K( O6 o U9 t: L8 Y: x1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
, s6 \/ _8 O3 B- X1 T: X: [& @5 l; T' O1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name./ U. p# s& f6 R7 X% a7 O: F5 L
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.61 K8 M0 A# ^: G; r0 M
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout5 x, H8 D; {/ l
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
# I) R3 T2 f/ O* o# |7 e1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.
. G- I7 [4 m5 o0 z8 F# P1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.3 x) T2 m. J! I: Y) d0 G
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties' }" I. b& W' A( O) ]) ^& b
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
( e* y3 x- i: `8 W8 r) S# K1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
5 y4 a6 I2 e- P" a% a1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
6 @3 @; r1 M+ E1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue0 Z7 W" j3 e; \/ y6 f9 [
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command" H2 d6 D( s" g2 a- ?% T
1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
6 O% h1 y+ c& F0 w1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error5 e4 r9 G. N8 D0 r& k
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
9 G( \. f( J" u1 o, P. T( X1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function3 ]; M* }$ G% o' f
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command./ v6 }) i: h t5 \* g
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
5 I! [$ z$ H( @1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group5 {4 P3 R: C+ S a5 H+ D
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
" Y4 V1 O d; ]# a1090689 ADW LRM LRM: Unable to select any Row regardless of Status! X; s, M% m, H4 |1 l
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
. h% u; D p: ~& w& X1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.2 ~3 g+ V$ j- N2 L
1091218 ADW LRM LRM is not worked for the block design of included project
: p- r- m& c+ L* H, z1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
' }$ R" w m3 T% C1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
5 {, Z! C1 M9 Q1092916 CAPTURE OTHER Capture crash
" Z) j! t3 X" K- A7 m" ~8 V" l( N1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database8 c% n3 B& A$ W$ ~9 S) I( [
U Y* H& U( r, H' U2 g: \
DATE: 12-18-2012 HOTFIX VERSION: 001
! F! \% O$ ]5 [' V' a===================================================================================================================================
8 z" {5 ]6 p7 \CCRID PRODUCT PRODUCTLEVEL2 TITLE' `: u* c4 C1 B1 m- p
===================================================================================================================================: n( B: g2 [: Y2 A7 i- x& y# K! g
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap' `- v1 l: g, M, C4 P/ B: L% U
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
& T; w" ?6 y2 Z( }+ Z825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted! C5 h, ^8 J6 {, ~
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
( L2 d* [" e4 h* G, e. z891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
2 l2 E, { {0 G2 ^9 |6 l0 z+ c898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
4 k# x) } S% d7 N& q0 v) Q923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
6 s8 t* B3 c' S, H938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
M- r2 R/ \6 w1 L3 A6 l0 X947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.+ e8 n, F9 @. f( o
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing8 b' {/ w$ A; d0 h! S
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
% P% F1 x) D! ~( f8 r! g: g981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.% U/ d; W; S6 G, g
982273 SCM OTHER Package radio button is grayed out6 j g2 i8 H: M. @# D6 v
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
* z0 N7 z* K) z$ U6 ?# e989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode' }6 M' o: T! R7 Y# W8 U
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).& ?3 ?# x$ y8 G: s3 S: k9 H
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections! ?# k: C8 @3 i, a# T9 j
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
, I4 `$ T' e9 a3 S1 ]3 ^+ x% o1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model2 m8 R$ d! i8 h) r
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
( \) N# q0 f s m/ S/ z1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
& P% _& @# }/ R6 D; D# H) ]1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.. q3 G4 D: `( t" K$ A; Y
1016859 SCM REPORTS dsreportgen exits with %errorlevel%# ?2 B* a. x. Z( r" e& y
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin/ V' O# H) e; B: P- a
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs( A! i/ i( N5 Y8 O! Q
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts9 s: r" b& U- S! ^
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-1404 O% f# I8 X9 J# E: N1 S' z. y+ y3 d& {- Z; I
1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
# X4 I# T, Y% Y; C1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button4 ^4 @% n2 q. B
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
7 }2 M: k( Q" L2 D1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
0 Q# p% `* T0 M4 W1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
& B" N* w* S- r# j8 v$ n. L9 g1035624 CONCEPT_HDL CORE Options pre-selected when launching base product' p3 B; `' Y" v% D/ k
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly6 [0 J0 K* v8 l p! b0 P( S( E8 ~
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.+ ?6 T) o/ p1 C+ }; s9 p* I) P9 f
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
( Y2 a+ \ o4 v2 Q& K. g! @3 p4 n1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
& n1 h1 m0 E9 V1038285 SCM UI Restore the option to launch DE-HDL after schgen. o4 B1 {9 r6 |1 I
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
$ Y$ D7 C* i0 i5 y8 A+ }/ k1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro6 [; ]3 B. U; h, n; _" T
1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected( |' t& o2 z m3 J8 a# E/ ~
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
: B8 l d/ d: X7 c- N1 I1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
. _! j$ S8 q3 m( q& ]" i1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.
) q8 E' {1 e( u2 _9 {; K1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu& r4 P1 t8 Y2 Z
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.. w5 P% r8 \3 O6 O4 N
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
6 ?/ ^! ]+ q! g4 T# k& f6 L1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory' i' v: X9 t2 ?& I i+ @
1043903 GRE GLOBAL This design crashes during planning phases in GRE.4 f, V* c9 T) i) C" O$ Q9 d2 U; c# Y
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached, N' B2 `$ @% E6 q. r: y- u
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
. ~4 c$ q8 C7 C1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
( o5 c4 k" ^. h! D* W1044577 GRE CORE Plan > Topological either crashes or hangs GRE
" t1 R+ U0 m' a2 S1044687 TDA CORE tda does not get launched if java is not installed
5 H5 Q0 t: K6 T' C# `1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
# N+ T# O! p* v$ _7 q4 m- W# B% _1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
, L H# T7 \8 R# W0 \1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
5 w6 k) c& k! E1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.+ z5 l4 O+ Q- R0 v
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
. C8 k6 o% m v2 ]0 W; n) @- l- L1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow ] j. Z4 T) e% v- `: }
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
9 W! `7 i" Y# ]( X4 w" C; r1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
% w0 t# _0 k# u c1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.1 b( ~6 U5 S2 F+ ]8 Y
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
: o; u- n) N. M5 o: k$ Z; ]) Q2 Z$ k1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5% W/ d- G0 c. U R: e2 Y$ q
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value; V1 I% `+ @( u* y5 y" c$ _1 C4 e
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
; _$ \. |" F, D" A1 U8 V& Q1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn篙.3 t' C2 X' _7 U
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.4 I) n: q& t# y! q+ |
1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.) D! e: ?$ K0 x
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes9 ~6 F$ q) Q0 G$ {% u: L
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.4 ~3 B4 S" c0 M5 S+ Z6 Z
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
: \; l' b. ~' j: B1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
+ o8 e& G: Q: G' m1 s, s1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
- |! r0 B/ [% W: _1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
6 K" Z: Q1 U6 s s$ L5 T0 `9 n" f# c1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.; x5 { \) H4 x% t/ c1 z2 a
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
+ _7 ~- w% @+ g$ L4 f7 \1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
8 U* _. a# Q9 |) g$ x- ~4 }9 d1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
* W% m7 @& i+ f4 u2 {1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
7 ^8 s+ _. m: g- b3 c9 q' m1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
+ Y1 r' t$ f7 U. U, g5 E1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down9 E! j Y, Q" G
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection9 V$ V1 b% A Y6 j# w; c7 ?
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
d3 Z2 n3 p5 R, g2 {' m6 S1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
( d- h1 a4 g4 S+ y) n1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline) A+ M: Z7 G0 D2 e- y
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.
& o, S+ J" q/ o |" E5 e: Z1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.
6 s- _/ g3 d4 y1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
: R4 f4 r8 w1 Z' o: H' y) Q1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value# ?5 y4 O7 H& A$ ^3 ]
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
8 C1 W9 l" M, i) t' |6 P1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
# k6 n7 t+ \/ K# C1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.- Z; i/ {( x& q2 T& Y8 B1 x
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
1 w9 [8 J1 Q2 M1 _( a6 ]: X1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
% f( Z# _3 d4 d* k$ L {1 U" j1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets' ~5 y5 y5 V$ T' o
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?/ O5 P) ^& _1 y
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.) \1 L' k$ b5 x7 R* U0 Z1 }
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished., a3 I9 B f% B; k
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
5 S, w, q- `8 [ f$ F% @1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
# F K* B7 O+ `% l2 a; T. O0 l1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
6 r4 B9 Q( m- J. z4 w( F0 {! j2 w0 q% U/ c1063284 PCB_LIBRARIAN OTHER PDV Save As is broken$ j: U+ x3 k0 b' W( T7 x- `
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs% u/ x5 T1 k* x% H% j
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.' F* d0 D# r' l$ L. S: e
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
1 x, E& a( Q8 p2 [1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design" p1 q5 Q& t; q
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
; A. b) ~8 l( y5 h; _' [1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.% W5 k4 a( c1 x2 S' k
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X) Y) F% N7 h' g* Z
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application! J* }& V& K" ?4 V; G3 H
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
+ M0 f3 @+ P6 w1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
O! u3 b) \; E- G1 Q6 r1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic, ]8 }$ H! V/ Q' ` T
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.( p# d; v c- B& C
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
) k- O. h, B8 E; X* E; ^1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 盧hange properties� command
4 z% H( G9 x# e8 E7 @- |1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended7 [3 I$ H( z7 B5 {" D8 y2 C
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067 h& L6 h! F& x+ S
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
) j' E! g& c8 M4 q' C% D1 l1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify) L: f3 C! k7 R: S+ K+ G3 ]7 z
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
1 n+ S1 b N. k' J+ p* g& L7 y( v1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes4 P% a# c. X$ h7 h7 G; r
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow+ l {, R9 y; ?( l* g: b' A
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal, n# z) Y A0 @7 B) Y0 a) O; `7 @$ M
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
7 Z0 i6 i& f: k1 A8 r) _1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
5 i1 n; U9 g2 ~ i. T) u1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
C$ D! o6 ~, _/ H) c1 i+ ]! ]1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
4 q, U# S' a3 {1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
4 o( [" @: A$ |3 K' u- x1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor1 {. R$ r \8 g$ u# J& q
1073464 SCM SCHGEN Schgen never completes.
7 P$ C! H P8 W" T1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
8 t. ]% C( R4 J) U0 R+ v1073745 CONCEPT_HDL CORE Import design fails
2 z$ `+ B( m) T- J9 {1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'" \/ I$ w, U6 v2 S- S# }
1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
G! Y! p2 y) E1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
: u0 Q7 Q* ]3 X" q1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter
: ^+ O1 V6 u3 ?/ O1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal( _" A/ E4 @% I( F o% ~
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
0 Q8 h) x5 `( V* m; _9 B8 X: Q1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI l! I) V# {" U6 _
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
$ g% j8 ?# {0 J! p5 q8 D1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer# e8 z9 M0 _4 u; Q+ K5 E
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
& S( ?. {0 O6 g% ~1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
0 X0 `5 i: b! I/ B/ y& H" v4 B9 {1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix/ Z4 ?4 e& m' m8 g1 P: t/ v# j
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
6 h: u! s7 W, @+ O9 W1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top2 |, G2 A2 t% C+ \- B: a$ l
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.! s* `* I( C$ e7 W' Q
1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
$ K1 K' Q% A( {8 E1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
' v: A, T2 x E& H1 }- z3 P1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
& C- m! x2 w% l Y6 j0 H" F1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database3 ?. k5 R+ W. P% k7 U; O
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
% c8 v/ V0 |, c& z3 K1 k. K- l0 l1077169 APD SHAPE Shape > Check is producing bogus results.0 {5 G% i' L! e5 v$ u: }
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.+ N* P2 G. Y5 c1 A0 i9 U
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
6 ~* U+ l, o5 W" g* Z1078380 SCM OTHER Custom template works in Windows but not Linux; x( J* [ U/ n- v' m
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.( q( S+ }. I. M* b1 c4 \
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide8 o) @4 e# b8 R1 U3 c% _% |: ~! G0 d
1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
4 t5 L' Z, b7 ` J1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"2 w Z+ Z9 C# d+ r% P6 w
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
1 F4 P8 P3 S7 f4 d1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control; A- l- W3 G J; p' R3 G/ H! N
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.2 t- N* X, b/ H3 X% L
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.* t8 I4 A; K h/ H$ [8 H% F7 g/ ?
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发表于 2013-5-25 16:00
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