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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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DATE: 05-24-2013 HOTFIX VERSION: 010- D( h% k( S% k# Z
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1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer- y& N' T. U5 i$ b+ b. m* O
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
0 m* b' G& b' ], o' y; Y/ V1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files+ u7 E) _# C0 J" {, L
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor5 {: H" ]- j* O% ?: q/ X4 J
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
/ k: A0 N0 e5 L: J+ C) e7 X' J1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
$ P0 l5 Z& W3 e1131775 ADW LRM LRM error with local libs & TDA
' `- m, I# I9 W1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
6 T/ }6 E$ w& Q1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
! X! T2 X: ^( H0 Q: h1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
& M- x1 K& l# \- @ _+ O3 d1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
5 p) t: H7 Z& @3 r1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
9 z3 H) h E! o" e4 D, M# C1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.% h, D7 { P$ ]
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor( O* s( |1 N! F3 h7 d1 ?: g* A( B
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
4 D) i8 p8 }9 K3 f" s2 P1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode. ]# H: {( e. H
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.: n* M# U. b3 i/ S6 i$ y
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
( \- n4 n3 K2 E; e" O1 w, Y/ o1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
% ~0 l4 C0 @) g- }1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
; K& e+ j( n+ U& [7 \: J1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor" `& r$ G: U$ D2 E- p1 n/ ^- i
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发表于 2013-5-25 09:24
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