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我的还是不行呢,
& w% u3 \7 m1 rTranslating E:/SPB16.3/Allegro/temp/project/S713OBX_SUBFPC/S713OBX_SUBFPC_V1.01(110503)0950.asc.
, {" f1 } _2 b0 J8 w/ ]Using translator version @(#)$CDS: pads_in.exe v16-3-85D 11/3/2009 Copyr 2009 CADENCE DESIGN SYSTEMS.- S4 G9 I; A, ?
Reading PADS ASCII file header.
5 b) |4 y1 Q7 U' k3 } Version = PowerPCB4.0
) [! u S, X, m Route Layers = 26 [4 s/ o0 @# f, ~
Units = METRIC
6 d: u3 M4 y' K% M$ v) \. { Hatch mode = Vertical / Horizontal- r$ Z& J$ r2 O1 U
Hatch grid = 0.100000, angle = 0.000000, anti-pad spacing = 0.0000082 ? h/ x; z/ N( R! I& d( W
Initializing new database.
" k" H( c3 c. d5 g2 `/ |- A Creating layers.. r1 q* m9 N9 ~- n" W A5 {
Reading PADS ASCII file body., {- p+ q H9 m" ^' ~2 \
*MISC*
; i. y( M9 ?2 j+ f4 ], p: h% v y3 T *MISC*0 N7 \- e/ j" ~- f! l3 i
Information: CSet 1_5_6 renamed to DEFAULT
+ H( }& T' c! O; M( {2 [' g% y O* G) i3 P
Warning: Allegro doesn't support default electrical CSets.
0 l6 {& P) ~3 G *MISC*
) R! z, Z8 O, [$ Q+ L& K *MISC*( y7 P" t; @! ^0 \& ]
*MISC*
. c8 \% }& N3 y5 o5 J& d! H7 ~5 k) ~帮忙看一下什么问题呢, |
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