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Cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至038）4 i0 L( z) I$ |" r
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下载地址：http://dl.vmall.com/c05sb7i5ed
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2 N M5 M2 _/ b4 o! V9 I1 jHotfix中只需要安装最新的版本即可。& x) O3 z8 x) C) Y# v
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Hotfix038对以下项目做了修正：; _5 Q" F: @4 i/ Z8 T
DATE: 02-15-2013 HOTFIX VERSION: 038
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics; }! p Q5 P" g1 m2 [* w% D( y
911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately( i9 [. Z7 S# a. x: M- Q& j V
995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.3 Z. S$ E, X0 e; {) V+ z
1005812 F2B BOM bomhdl fails on bigger SCM Projects7 Y D3 v) a# p
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.# L: ?# H* B f! K; ? u% p
1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer- w) p. i" M. y E
1065636 CONCEPT_HDL OTHER Text not visible in published pdf6 G+ s/ `& \ V) \
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts7 k8 Z! T3 K( L
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
+ l6 l |$ z( a! Q1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
) b! M0 `2 j! ^* L; l1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher+ v. L e* o7 K9 y3 C
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.% T5 y: J* Q4 @! W- E
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
# A' R- u! p; ^9 J! t: I1 M q/ Z7 ~1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
: R+ F* T8 ^5 H1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3' M4 j6 v* D1 _5 ]3 \% O
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
6 E5 o- y+ Z( G3 a, z- C1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
, a- q3 I. R, {" z1 j1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.: H, N7 @& J3 {1 m0 q3 |
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff* G' d j, o+ \4 b( Z3 x+ I- z5 U
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
2 m( N4 s m0 i% P1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
( j6 o! f$ j( T# G7 \! n6 `1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.4 i4 m9 P! q1 G4 l9 C' ?
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.( s1 @7 T+ ~/ E' T5 ]
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
4 p: A3 |& H2 M5 N" d1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
& d; `5 h# h! Y/ S8 V/ z1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
2 J4 e' `! p1 S1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
' x' f7 L3 R; w# P/ ^# e- }1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
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发表于 2013-2-24 21:41
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顶起啊 好家伙前几天才看到28的 现在都有38的了
