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本帖最后由 紫菁 于 2017-9-14 11:21 编辑
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; x7 z% Q7 r; M& g( }下面链接是Cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！
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Hotfix057更新的内容如下所示：
" t- u. ]% P ?9 N6 E! n% v1 WDATE: 12-19-2012 HOTFIX VERSION: 057: b: v# I6 t% _% h5 P7 P0 \8 ] B
===================================================================================================================================
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===================================================================================================================================
g$ N9 W) F2 o1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
; y( i; n/ T) j: Z6 N+ Q) R1082509 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.
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DATE: 12-7-2012 HOTFIX VERSION: 0566 y( M0 b; v2 E
===================================================================================================================================: Q# u5 M+ f" v$ q8 d) n$ U
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ a' W! V# [3 l+ ?===================================================================================================================================
- ~5 ?* I2 h/ D8 \9 h* E825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other8 `, Y$ D" A/ V" v0 r, {
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash0 s1 F5 E7 P: t2 F1 V
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide- [' v" r5 O8 L
873917 CONCEPT_HDL CORE Markers dialog is not refreshed" C" P6 i6 s7 m* Q& ]9 _7 w
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License, k" Q3 Z3 t- K
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator5 h$ D+ ~7 s0 k9 q- }# O
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic3 ^" o0 `& D! F* u( y! i
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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