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本人Layout之后分割好地和电源层,灌铜时出现这些错误:
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THERMAL RELIEF ERRORS REPORT -- FPGA2.pcb -- Fri Jan 11 21:44:01 20132 f C/ A3 L9 K' b- h
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6 M4 k- r' f. c2 x Drilled pads with Nondrilled pads with
9 q7 P' J6 H1 B$ H, Jless than 50% thermal extensions less than 50% thermal extensions1 S$ n* C+ n( j& a% p5 X8 s% D
7 Q- w& \3 w; h T7 K0 J3 R' aReport of Thermal Spokes Generator.
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On GND3:
* C+ G# H! v+ l& H5 H3 g, n (2506, 775) # = 0
8 u0 f5 ~/ l. g+ D/ S [9 s: W$ ~ (807, 454) # = 0
4 J X+ E, O' |; a7 D (3125, 750) # = 0
- E% ]* z' r3 z- U: \: \ (418, 189) # = 06 q7 p/ d) l; _) _( s1 T% }& v2 @
(2199, 749) # = 0
7 U& d9 B: ~9 y, ~% N7 T (1178, 648) # = 0
2 q: J- p; _( v9 ^% G (1295, 800) # = 04 U6 ^3 s' C5 J' Y$ P1 ]# m4 _4 K$ G
(1256, 839) # = 02 i6 b& t: p/ S4 j! u
(1763, 878) # = 02 k) P, r8 ^6 X4 Z" t; h
(1646, 878) # = 0( T3 o: ^ D, w, x3 j. P
(1295, 878) # = 0: Z$ o" v% T# H) p5 J. C
(1295, 917) # = 0
9 p4 y1 Z" {% y/ }0 v* L& y (1256, 956) # = 0; _- i; o* d {
(1685, 1034) # = 0
/ K- C! g r$ }, |! V. C2 y (1295, 1034) # = 0! [' ^: s% V1 Q6 Z
(1646, 1073) # = 0
& V" O8 j% o, w4 z% b9 l' \4 x' N3 D7 D (1295, 1151) # = 08 R% I3 k+ ~# v6 H5 A. i9 X
(1490, 1231) # = 0
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_* W1 m# b, X Y, ~Total Drilled pads: 18 Total Nondrilled pads: 0
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( X# l; B5 L6 W Q. ^7 ^Report of Violating Thermal Spokes Remover.
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: T6 Q, L2 l+ S) h) ?On GND3:/ N# R5 Y+ T: o" d: z) @2 o( P1 S/ D% r7 ~
(1373, 1151) # = 0
2 F8 x- l5 D% g3 O/ e (1490, 1151) # = 0) _/ \% b) |6 l& g8 l) T
(1529, 1151) # = 0
( v4 k2 A3 Q4 s$ }, k! {0 l# k (1568, 1151) # = 0, [- i0 d9 }: ?& C
(1373, 1307) # = 0
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On Power:
+ S# {. n3 p6 F1 P! H) O3 S (2086, 1220) # = 0
: g, h m' M, {; c1 k (2334, 760) # = 0
) {$ a+ m1 H$ y5 `- } (1178, 683) # = 0' B4 f. A0 ~7 v: G
(1139, 683) # = 0$ L$ r1 x% @+ o; A5 M
(1728, 882) # = 06 ~8 I, S2 L _; m: A% [
(1143, 761) # = 1
; V4 ? q; z. |7 i; c5 y (1218, 1181) # = 0
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6 a! |& X& l' \% J; ITotal Drilled pads: 12 Total Nondrilled pads: 06 ^5 D, o L' H0 |7 {
不知道 这是什么问题,如何解决? |
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