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在原理图package的时候出现Parts DataBase中没有某个符号的Part Number是什么原因

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发表于 2012-12-19 20:37 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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我在原理图package的时候出现Parts DataBase中没有某个符号的Part Number是什么原因?$ S% P; n- d* w
检查symbols和Parts都有Part Number啊,错误提示如下,请高手帮忙解答。
6 p( x* Y, E  e+ o/ F. f
2 u1 h- D% o  z+ U6 h: G- }; e' S( \. ~! R8 F
ERROR: There is no Part Number: FCT16245 in the Parts  p/ S3 X( t# Y2 ]& X
DataBase for symbols with Part Name: FCT16245 and Part Label: 16-Bit Transceivers.
* b1 |% w3 l3 L- [/ i4 z% N7 m[Please add the Part Number to the PDB either directly
) G; T6 ~& f* L. M0 P( D$ V& ]1 wor by having the project file point to a PDB that contains it.]
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发表于 2013-10-18 23:42 | 只看该作者
hittjd 发表于 2012-12-30 15:03
: c! l( R9 e% }4 D3 Y所以器件都做part了,而且可以确定是从part view里拖出来的。。。

$ Z8 f; j9 y/ ^  Q: z1 j& J请教个问题,我在做part时,遇到下图的情况,好像是symbol的pin(s)没有映射,请问如何设置啊,谢谢

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发表于 2012-12-22 22:30 | 只看该作者
删掉有问题的元件,重新调一边进来,再PACKAGE就好了。

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发表于 2012-12-23 19:34 | 只看该作者
打开中心库对应器件的symbol,检查左下角是否有Part Number项。

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发表于 2012-12-24 09:23 | 只看该作者
看看库里的Part Label,这个也需要对应的
# L  V& A. V$ B8 j9 p7 V

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 楼主| 发表于 2012-12-29 08:54 | 只看该作者
sunny_sun1022 发表于 2012-12-22 22:30 + B/ N, e1 R  e6 r5 i8 p2 B3 H
删掉有问题的元件,重新调一边进来,再PACKAGE就好了。

4 F, S% Y; N& R2 ~+ w0 d2 i  t6 Q1 j# n试了,不好使。。。

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 楼主| 发表于 2012-12-29 08:54 | 只看该作者
simhfc 发表于 2012-12-23 19:34 3 D! k6 [* `8 @2 u
打开中心库对应器件的symbol,检查左下角是否有Part Number项。
$ r. v2 i' J1 \  S
有,这个肯定有的。。。

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 楼主| 发表于 2012-12-29 08:56 | 只看该作者
zxli36 发表于 2012-12-24 09:23 ) q- T1 h3 d1 D- R# P6 h
看看库里的Part Label,这个也需要对应的

9 x$ ]7 n+ k5 W7 [7 T$ {请问怎么对应?我原来的Part Label跟Part Number不一样回来我都给改一样的了,还有part name ,还是一样的问题。。。

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发表于 2012-12-29 09:02 | 只看该作者
本帖最后由 zxli36 于 2012-12-29 09:03 编辑 ( _( c5 ~# M' I3 ~/ j3 n
! s# F: s0 t3 R1 j4 [$ U/ g3 M( v
对应是是你的DxDatabook里面的这个项的名字要和你库里的Part里面的这个项对应起来。2 Y% O4 C; I* S
比如你Dxbook里面的器件:% o# {8 ], t: p1 q( y" t
PartNumber: IC1234PN/ U- N; |2 h1 C
PartLable: IC123Lable
) S% I5 w, A* j+ Z- [PartName:IC123Name/ @  }3 P& j3 Y- |* a+ k0 K( [
这是你的库里的Part也需要想上面的那样写名字

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发表于 2012-12-29 09:04 | 只看该作者
能不能把你Package时的信息发上来大家看看。

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 楼主| 发表于 2012-12-29 09:49 | 只看该作者
zxli36 发表于 2012-12-29 09:04
6 p$ ~5 B0 p: ^( n2 K+ L: }! Q能不能把你Package时的信息发上来大家看看。
, e$ n! K0 g0 H7 Z$ G% l
Package时的信息如下,总共有二十几个问题,几乎所有器件都有问题,这个问题困扰我很长时间了,麻烦您帮我看看,非常感谢
" r0 d* n' E$ d4 \* Q& E; a) i2 A; M! {6 a% K9 e- _% F2 ^6 [7 t
-------------------------------------------------------------------------------------------------------------------------------------------------------8 f5 s( A1 p1 y" }' T7 ?
Started C:\MentorGraphics\7.9.3EE\SDD_HOME\wv\win32\bin\packagerui.exe F:\demo_dx\demo_dx.prj /d Board1 /nobrowse /config "C:\MentorGraphics"2 p6 u/ O- O- m, f  g0 u

; i- |0 Z/ ~& U+ OPackager Version: 020806.00! C# N3 p# Z7 h, u
$ N& P' N! U  y7 G5 H
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"
: x3 d9 d( Z; a. {% u4 ]% s$ B' q- v
The Common Database is at "F:\demo_dx\database".+ n; r: n, ~5 _' ]. E! h; f
7 g: Q3 T0 O  c$ O# B
The Root of this design is "Deme_Root_1".! |3 T! Z3 b9 u& ]; M$ s4 `# B
1 B/ e/ a: w8 P8 G# g6 V4 t* |! `
The Front End Snapshot of this design is "DxD".* {5 `- O5 l& ~: @. ^

( ]- [2 [! ~4 g+ rThe PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
1 I  u/ b& U, Z6 @7 Z. {" D5 u. y2 Q; T3 |/ [) ?. F8 P6 y8 }3 t6 P
The Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc"." M+ G& ~0 N9 K7 a" Y
, w0 T8 E9 h( N
Unable to determine the Disable Repackage status.
/ x. [1 B9 d4 m: ^  l) L!Repackaging will be allowed!7 F* b3 g* M( ?

' r/ D5 Q$ q2 _8 t- o5 uThe PDBs listed in the project file will be searched to satisfy the parts
6 ^+ |& I! s  _( p/ W" V. T* }requirements of the iCDB only for parts not already found in the, h9 ~6 b1 t8 a6 `) {7 b
Target PDB.
# M' f; F) ?; W- @' }0 N. T' G8 d; V! s. Q. w4 ?) h+ K* `
The AllowAlphaRefDes status indicates that reference% q& [' o- J# u- {  P* ^
designators containing all alpha characters should be deleted
( C0 B( M" N7 t3 \3 e3 V0 F) aand the relevant symbols repackaged.
. k; {7 S( ?7 B7 w9 V( r! {# S: M2 i( y" F
The cross mapping of symbol pin names to Part Number pin
" f, g( M5 g" o  N% e4 xnumbers will be checked for packaged symbols and mapped correctly4 C9 k* f7 G" Y3 }$ D
for unpackaged symbols.- c3 F- t/ @9 J! U- A

4 S' P7 [& Q$ ?, w6 `6 tProperties that have been checked off in the Property Definition Editor" k" d) M* p, Z! S! k
found at Library Manager/Common Properties will be checked for value# `& ?" l/ c; \+ k9 Q1 ]8 R
differences between the PartsDB and the non-null properties on symbols.+ r' i7 c, s- a+ u& w" P1 L
Those properties checked off (other than Part Number)
. }! v  i' k/ ]2 S* W+ qwill not be transferred from the PartsDB to symbols.
. A6 x' R' ?% w/ M6 p. VThe following properties were checked off in the Property Definition Editor:
, V6 R& e, P3 H5 k7 g7 \"EPFIXEDWIDTH"1 w" K. S; g4 v. |
"EPFIXEDLENGTH"
0 c1 O5 t- L: S: U* k; n+ m) Z! x, w"Term"
$ g. I3 C7 c( t) q: c! W"SIM_MODEL"" C5 j8 Y, R% {8 H, E
"SIM_MODEL_FILE"* C  G. c3 y& ?2 ?; S1 K
"Array Component"
9 }  k4 y" R3 X1 `"ICX_PART_MODEL", p) B7 a& Z. q) e& U
"Use Verilog"
6 u# t2 g7 {" j5 [* t6 a: O# }1 x"Order"
( T0 y9 m2 O# V"Parametric"2 Y" [" w0 d( c. o+ S
"Value2"
  r3 x6 w: `: m1 i"Tech") C* g& [7 v. a1 ^+ d5 m
"IBIS"6 N$ F. _4 }4 W& l
"Part Label"( ]% O3 ~4 W0 k& k
"VHDL Model"
! F! s4 A' C$ P# A% d"Verilog Model"' E, i$ q2 f: I7 x5 |. u! c
"Cost"
; V8 ^/ N8 Y' b"Tolerance"6 g( ^, V: ?8 [
"Part Number"
: B5 h3 O) x0 g! [! a# d"Value"4 `! E! J! p9 p1 {  v! t$ G
"Part Name"
) u) Y" p; o/ p( M. b* \: P
7 e, T( @; ^$ m1 w# [/ C$ F$ ?: e+ G; f
Testing of Packaging is being terminated with 22 errors and 1 warnings.8 k1 d: j3 F# J+ `
Design has NOT been packaged.( G$ n$ o( f/ p' N

' D  r! n2 A4 \0 e4 }Writing to Log File: Integration\PartPkg.log! o0 }' C, |. Q1 y. p) @

4 Y% m6 z# \$ t' p+ ?! SThere have been 22 errors and 1 warnings.5 d! _2 Y( v" n2 [* c0 p

' O/ a5 H5 i; b) c( b" m# X///////////////////////////////////////////////////////////
, f) p) g( V/ t$ m///////////////////////////////////////////////////////////
: e$ E' G/ e# o2 c& L8 A: `* H///// The Log File will now be copied to this window. /////
) V) w! [. W  s///// Therefore the data above will also appear below /////
4 b5 b- c2 ~" k& R$ H///// with more specific error and warning messages. /////
9 K  `' N( V& O% M! T" \4 ^///////////////////////////////////////////////////////////4 _; ?1 a1 o- b% B, W
///////////////////////////////////////////////////////////
4 f- a% F2 o% \0 |' A( k1 h# x% e" W2 u; `' ?' H* q/ z' e9 c
. F/ N( A) Q/ O; ~+ e7 q
Packager
6 _- x: r) g1 g. R8 [: ]2 R--------
9 k6 e% i1 o9 B  h. i& N& e4 u4 E6 x9 {1 _
09:27 AM Saturday, December 29, 2012( \: x$ P) d( ?! \, V
Job Name: F:\demo_dx\demo_dx.prj2 D* t/ C/ v1 T; O/ E2 V
. l, ~; W! \1 y9 \9 ~

0 \9 N( z6 D9 ]9 }Packager Version: 020806.00, C/ e/ ^* M  m# B6 i0 h, X6 E

0 [7 i0 b; v2 u. K4 A2 L7 b6 [Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"; X; f! n' e/ s; @: O
1 L( Z% I* D# O
The Common Database is at "F:\demo_dx\database".
0 _1 m+ M4 ?) `# g- o+ _# R, U) O  ?) K6 [3 m! Z8 i) M( t0 ~
The Root of this design is "Deme_Root_1".2 P5 R- X. p. F1 K( H
, U) b5 P5 H  }6 ~
The Front End Snapshot of this design is "DxD".( }3 j; `) P& N  P5 R7 S* x
/ i$ t! x0 e) p4 o
The PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".6 \; L- l/ `' l+ s

0 L5 C2 H) j9 s7 Y' YThe Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
! n  i' e, r: W9 w/ P' [7 I: M. i2 ~$ e
Unable to determine the Disable Repackage status.
3 z$ k' F; }! Z!Repackaging will be allowed!
, p3 \. e; m. Q; ]; Q
8 j) B9 B4 \+ d4 NThe PDBs listed in the project file will be searched to satisfy the parts
8 U- D8 _8 P/ `& k: q% n* ^; c8 yrequirements of the iCDB only for parts not already found in the
! E% @. v8 [! D0 e& {Target PDB.
* g9 Z# Z3 N( n' l
/ v% z1 K8 @! t# j  |The AllowAlphaRefDes status indicates that reference! i0 U1 [1 _% p' @+ L
designators containing all alpha characters should be deleted
! S# a0 A' B' q' \5 h: `" pand the relevant symbols repackaged.
/ O8 V, ]1 q. g0 U
! \; v2 H; H$ u' Q1 ^The cross mapping of symbol pin names to Part Number pin7 H- _/ x7 ^; o7 Y$ I6 }
numbers will be checked for packaged symbols and mapped correctly  J, a3 y' a* X1 m2 g; M+ ?
for unpackaged symbols.' i1 Z% P. [; b- }0 h1 t

/ f( D3 O0 L% qProperties that have been checked off in the Property Definition Editor9 E! O3 V- p+ T( _6 Q8 |+ r: j
found at Library Manager/Common Properties will be checked for value' ]" Y2 `9 Q: i4 Z$ I
differences between the PartsDB and the non-null properties on symbols.
% f: ^6 M  a8 u0 W3 N! }- SThose properties checked off (other than Part Number)
9 h. t! x; W9 Z, F8 j7 lwill not be transferred from the PartsDB to symbols.7 ?9 h+ N8 ?, I* |" \/ I
The following properties were checked off in the Property Definition Editor:
  r' H2 ?6 c# d7 L+ P/ t"EPFIXEDWIDTH"$ E  N9 `5 F$ s
"EPFIXEDLENGTH"
  T" O1 ?, h) T+ u$ P! G5 v( z) Z"Term"" E4 o5 }, [% E: r' r
"SIM_MODEL"
" I5 `; I$ D! o% u& u' x"SIM_MODEL_FILE"
! f3 o: j5 S' c6 S8 d"Array Component"
( F+ k! ^, y" r, E4 @- G' G# |# u"ICX_PART_MODEL"# }! {1 _/ U1 S, U) @% b: m
"Use Verilog"
5 \0 R! x- `9 i' E2 I) Y"Order"
8 x, G& R( r# |  o: t6 h/ u"Parametric"2 J# o& j, U4 |1 u7 h
"Value2": |0 @" K, ]7 J! t5 d
"Tech"
. T0 M) J7 i; S"IBIS"
" W0 f- e+ ^( _/ T"Part Label"
. Q3 O$ I. e' D* A0 W* x* Y"VHDL Model"( F6 D2 ]8 c/ D
"Verilog Model"2 J5 [' k9 g# u: N! _
"Cost"! A  V9 h% }0 e6 j$ b/ y2 S* Q
"Tolerance"
& h! `- n9 i0 E# [5 |4 K"Part Number"' @- d5 W4 E& r8 `
"Value"& k, x- ]+ @" \+ A% g
"Part Name"
% R. ^7 }4 a, Q. @
) D; U. s" \! f6 QChecking for errors in the ICDB...
6 s7 X$ P+ P' T* o
: n# g1 ^  P7 @1 N) PNo errors found. Proceeding with packaging...
' V& F2 @8 J  T8 y" R, v3 i. u3 G# V. P( T& I4 |  S
3 A# q0 v$ q& y5 T9 G
- R! N, u0 D( K7 C5 D* |/ \: k6 t
Common Data Base has been read) h6 M0 \" U% E4 d+ Q
# r' l4 ^1 ^0 b; ~( l/ w
Target PDB Name: Integration\LocalPartsDB.pdb* X# Q; R! ~% \9 B8 I
2 z- p2 w/ w- ^2 ]! f4 _# d# v
WARNING: There are no PartsDB partitions from which to extract parts.' @2 V6 [, W3 H+ {; X: m6 p4 U. [
Proceeding using the data in the local PartsDB "Integration\LocalPartsDB.pdb".
5 E+ J) d/ V8 o& N' n' i- M: S
5 l  O% Q/ _/ R! o+ L8 }3 g2 E+ T( PNumber of Part Numbers: 21
( u5 u6 Y9 J: }$ Z  Q- {Part Numb: BNC_1 -> Vend Part: 6 o, L  x0 r; m+ A/ b
Part Numb: CON_EDG_64 -> Vend Part: / W. G  E/ b8 d6 U% D3 R
Part Numb: C_P0.01pF -> Vend Part: 3 R4 Z7 Z$ e2 a* G8 \
Part Numb: C_P3.3uF -> Vend Part:
- O( f% J' X4 n  d' w' P+ DPart Numb: C_P47pF -> Vend Part: " o) L( C0 T: y2 q
Part Numb: C_0.1uF -> Vend Part:
9 N. V+ c, v* b6 q0 LPart Numb: DG419AK -> Vend Part:
; @* f0 C8 C% k7 Z! M' [Part Numb: EPC1064 -> Vend Part:
1 h3 _- q0 i5 E6 Q6 e4 J, gPart Numb: EPF8282A -> Vend Part: % ~+ W, [0 I! z: e2 t
Part Numb: FCT16245 -> Vend Part:
, }$ b8 W7 ^$ @; B8 a( \Part Numb: LED -> Vend Part: % M4 d. q' m, {& \. r; K% S% X
Part Numb: L_50uH -> Vend Part:
9 z& y5 W, \( s2 n% ZPart Numb: R_2K -> Vend Part:
( n# O5 K1 m! m3 V6 vPart Numb: R_10K -> Vend Part:
/ b& W; h- M+ }6 kPart Numb: R_100 -> Vend Part:
6 x- V+ u: v) v' Q1 KPart Numb: R_220 -> Vend Part:
3 n* S1 E' ^8 t$ fPart Numb: R_510 -> Vend Part:
( T7 p% i; e2 y3 Z0 _Part Numb: TC55B4257 -> Vend Part: ( G& D0 ]+ A3 z3 l' U: Y/ I9 X
Part Numb: TLC5602A -> Vend Part:
: E! D. _8 g8 d5 a, QPart Numb: 20L10 -> Vend Part: & V% n( u) _% U* a
Part Numb: 74ACT574 -> Vend Part: # W8 O$ A& K+ k+ \( w, z9 W7 }! J

# l+ D& z' ]3 i5 p& n4 INumber of Part Names: 1
! D0 K0 a+ R/ n% O/ Z2 DPart Name: TLE2037A -> Part Number: # a0 V' \8 ]0 c7 a
7 ]7 f/ E! v7 a5 o+ R5 N
Number of Part Labels: 0. B9 ~" Y1 t' q, K$ `

; O  B0 }% i& r6 ~9 T8 ?
9 ~3 n9 f) I2 @: YChecking for value differences between non-null symbol properties and PartsDB properties,
; t$ i  u) M" a2 G( Sbut only for those properties checked off in the Property Definition Editor
0 I0 Y3 X# j6 b( _% r* M( ]# y9 F# l
Checking the validity of the packaging of prepackaged schematic
4 q1 ]$ N! h% Rsymbols. Only the first error in symbols having the same
- h% u+ `7 U3 C* k" a( D8 cReference Designator will be reported.
5 Y, g, d" B& }! |2 Y
, \4 T' \+ C0 [3 Q3 k/ qERROR: There is no Part Number: CON_EDG_64 in the Parts2 L9 G, [) {* n3 N( ^4 m
DataBase for symbols with Part Name: CON_EDG_64 and Part Label: (null).) {- e7 T; n. a/ W4 j% {
[Please add the Part Number to the PDB either directly
# W' P. ?1 o+ L4 O: j& ^+ Vor by having the project file point to a PDB that contains it.]
& r, d7 [. z+ L8 Y; V9 [+ B# ?The relevant symbols are:
' X% C$ z1 {( E+ ]0 s6 w: h  ]/ y' ^" s- M9 Z7 s
Block Deme_Root_1, Page 1, Symbol $1I41 & ?6 r( ^0 V+ s5 t- |4 H
, A& i& \& ?$ s; `$ @2 k% Q
ERROR: There is no Part Number: FCT16245 in the Parts
) r+ R0 a# q6 A4 i( i. a" T4 |6 F( q/ sDataBase for symbols with Part Name: FCT16245 and Part Label: FCT16245.
1 d' P0 s9 j- X( |2 Z0 p1 d[Please add the Part Number to the PDB either directly
4 y0 ]5 N- d* @3 n& J' {$ {# y5 L) Z% [or by having the project file point to a PDB that contains it.]
- p8 b7 N# _6 r+ N; E$ U' q9 ]The relevant symbols are:4 ~& f1 M, o) Z4 [1 b- x) H/ _: A
  ~' @: ~! c7 o1 s, r# Q) n  z( C
Block Deme_Root_1, Page 1, Symbol $1I1277
5 |# X' F# a( y3 d! B( b; l Block Deme_Root_1, Page 1, Symbol $1I1424 $ N. U  p  w' i8 _: a2 W! m
Block Deme_Root_1, Page 1, Symbol $1I1395 * C8 h! [' j; F( S
Block Deme_Root_1, Page 1, Symbol $1I1366 3 g+ J+ G( D3 q% Z
Block Deme_Root_1, Page 1, Symbol $1I1337
, t4 e/ b  |1 O2 Y6 t, q7 E Block Deme_Root_1, Page 1, Symbol $1I1308

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11#
发表于 2012-12-29 10:44 | 只看该作者
这个信息写的很清楚了,只能根据这个信息查先。真不行了就要发库给别人看了。

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发表于 2012-12-29 18:05 | 只看该作者
There is no Part Number: FCT16245 in the Parts0 d8 m8 s4 R& V0 H9 C8 [
应该是只做了Symbol和Cell,没组成Part;
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所以说在实际工程的DxDesigner里,DxDatabook要用Part View,不要用Symbol View。

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 楼主| 发表于 2012-12-30 15:03 | 只看该作者
simhfc 发表于 2012-12-29 18:05
0 H: l, F7 e& k6 P+ r6 S  gThere is no Part Number: FCT16245 in the Parts2 t7 l. V0 J4 F$ L% Q- k2 O3 x  p4 Y( K
应该是只做了Symbol和Cell,没组成Part;
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所以器件都做part了,而且可以确定是从part view里拖出来的。。。

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发表于 2012-12-30 22:41 | 只看该作者
做了Part之后,有没有改动过Symbol或者Cell的pin name / pin number ?
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比较直接的办法是删除那个Part,用现有的Symbol和Cell重新建一个Part,然后去原理图里更换。

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 楼主| 发表于 2013-1-8 19:47 | 只看该作者
zxli36 发表于 2012-12-29 10:44 0 z2 P9 t' s" Z4 r' \! l' ^
这个信息写的很清楚了,只能根据这个信息查先。真不行了就要发库给别人看了。
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能给我发个你的邮箱么?我把原理图和库发给你,你帮我看看吧,拜托了!
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