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16.6 的 hotfix 出現囉

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发表于 2012-12-17 12:49 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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{:soso_e100:} 4 ?* i% S2 B, b8 r* r$ H2 \
16.6 的 hotfix 出現囉 ~~ 14 Dec 2012 SPB16.60.001, Version: SPB:Hotfix:16.60.001~wint   

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收藏收藏 支持!支持!1 反对!反对!

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发表于 2012-12-17 14:46 | 只看该作者
是不是16.6BUG多得受不了了?{:soso_e120:}

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发表于 2012-12-17 14:48 | 只看该作者
还在用16.5

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发表于 2012-12-17 16:50 | 只看该作者
期待这个hotfix

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发表于 2012-12-17 17:52 | 只看该作者
更新了神马

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发表于 2012-12-17 18:18 | 只看该作者
求链接

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发表于 2012-12-17 20:05 | 只看该作者
ASI也可以下载了,Allegro Sigrity SI

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8#
发表于 2012-12-17 21:13 | 只看该作者
本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑 ( y6 }' \+ f" S
& ?. t7 k5 Z4 M  k
别的地方找到的更新说明,其实干嘛老是跟着公司更新软件啊,我就觉得16.3挺好的,功能就很好了
% b: F! N. c7 N. a- sDATE: 12-18-2012   HOTFIX VERSION: 001
$ l8 C! _: n- B3 B; S  p===================================================================================================================================
0 @) c+ M% o5 d) s+ RCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
% q" |! K+ b/ I===================================================================================================================================+ M) ?8 [/ A" Z. I1 _8 P" [
501079  ALLEGRO_EDITOR MODULES          Enhancement for Module swap function similar to component swap; ]* {5 O" n8 k1 O, C3 j( {
745682  CONCEPT_HDL    CORE             Attributes window requires resizing each time DEHDL is launched- |" w7 I8 b1 j% P; X
825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted4 g' H+ V# t$ ]5 ^; n/ i
871886  CONCEPT_HDL    CORE             Browse button in Signal Integrity window of DE-HDL option causes program crash2 ?4 H" N" Y" b$ S2 F
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments4 @2 y# U! S/ @
898029  CAPTURE        PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore0 `1 S+ l5 D" ^' Y
923210  CONCEPT_HDL    CORE             Search with multiple properties does not show all properties
8 a' p  i' @+ v3 l: q* m. C2 [938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
4 Z7 Z; `0 L5 R/ ?+ B$ K  g* U947451  ALLEGRO_EDITOR INTERACTIV       Allow the tool to select multiple shapes when assigning a net to more than one shape.# T- H9 ~' ?8 ^3 S- ]# g/ A
968646  ALLEGRO_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing  @" N% \: f  `% o% h) [7 b0 D% K' E
976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
' n9 E3 w; @! j, y: F* |8 A! K981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.8 w- @7 o# K5 Q. ^1 h& S
982273  SCM            OTHER            Package radio button is grayed out& c6 t$ l# n  I
988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command* I& }& T( ]8 O7 s6 p
989471  ALLEGRO_EDITOR INTERACTIV       Functionality to zoom to the selected object in Pre Select Mode& Q! Y4 a$ h8 R. i5 A  i; h- ?, a
993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
2 ?( U5 _3 Y8 H7 r+ r% L996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
4 Y! v7 [3 s. u1 Z997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
& }, P9 P" P+ w: T! A1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
% ]$ d2 |- v9 L1 h0 M: x1010124 PSPICE         SIMULATOR        Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs" z2 P" \% V$ N, z
1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg; [" L, ~5 }' K2 v2 ?! {2 y$ V
1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
5 Y. e$ p$ O0 G4 Y' u% m/ V1016859 SCM            REPORTS          dsreportgen exits with %errorlevel%
0 \, W7 o) s6 o/ q, L1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
. U$ B. Z! r1 M* d8 A9 R1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs* w9 q) Q; b0 E
1020798 SIP_LAYOUT     SHAPE            Shape not voiding on layer 2 causing shorts
; w% f8 C' U  w; O1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
; ^$ }8 h7 e+ K! @1023774 APD            WIREBOND         After "xml wire profile data" is imported it isn't reflected to actual wire.) n2 {/ G' k. e1 Z, O
1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
' l9 n/ \, Q) D" @! U, V1024239 ALLEGRO_EDITOR INTERFACES       DXF pin location is moved when I execute DXF out
7 g5 M; X5 c4 m3 W8 r( ?. g1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
" d/ k6 A) w- ]* y0 x6 V1 c1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
  x2 r2 I- R& l$ ]9 o/ \1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product! |8 w  t1 x- U% s$ I  [# w% f
1035896 SIP_LAYOUT     ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly8 a" M1 C' x% N$ K7 D
1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.( {  m4 |9 P  y2 Z9 s& O' U
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)7 Z6 j9 v4 z* ^# d4 t7 `
1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
# I0 m: z7 _- {1 G0 B$ Z# s/ e1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
! \1 d$ R: {1 H+ D1038371 ALLEGRO_EDITOR INTERFACES       Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."% H+ x. }: X) Z3 E2 i9 j
1038577 ALLEGRO_EDITOR DATABASE         Modifying Void crashes Allegro
  |' K- Q0 k& v+ H- g3 V1039112 ALLEGRO_EDITOR ARTWORK          Antietch and Boundary layers deleted when Match Display selected
5 I2 Y) s: d  I+ T+ a; k8 U1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing8 g4 {3 S4 Y$ o! h
1040653 ALLEGRO_EDITOR DATABASE         Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.' m0 ~+ K( D/ X4 ^( ]7 Q3 e' M
1041368 APD            DEGASSING        The Degas_No_Void properties assigned to Cline does not work.
! e/ t# ]1 w0 N1041864 ALLEGRO_EDITOR MANUFACT         Allegro crashes when opening the Backdrill setup menu) [7 V6 n" S: U
1042199 SIG_INTEGRITY  SIMULATION       Waveform list was not refreshed by switching tab.
; S- T/ f$ U/ O/ t1042348 SIP_LAYOUT     STREAM_IF        GDSII export includes the full refernce path, breaks CATS flow
# n% @2 v' P. b/ d: v8 T5 t1043861 SIG_INTEGRITY  REPORTS          Derating values are NA in bus simulation report when derating table is not in working directory
: M2 a  L9 l+ G* W- _& S1043903 GRE            GLOBAL           This design crashes during planning phases in GRE.0 _5 v5 g, v( s$ p+ F8 k* P
1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached# M5 H* ^- B/ E5 C
1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory7 O# y* d4 x- P& O
1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
/ O" R0 S* E& r4 h6 X1044577 GRE            CORE             Plan > Topological either crashes or hangs GRE- b9 R5 F7 P1 y
1044687 TDA            CORE             tda does not get launched if java is not installed
. |( h. W- t& x2 N# ?; M1044754 SIG_INTEGRITY  SIMULATION       Incorrect waveforms when simulating with stacked die
3 M# f1 ?  A3 ?% K1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form./ Q" V" t# i" j7 z
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
! z$ i5 a: g$ q. W1 Z1045863 CONCEPT_HDL    INFRA            Customer had the crash several times when they run script with SPB16.51.
' z& d% ]2 N% S1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.. y  `& ?9 H3 \- q
1047590 ALLEGRO_EDITOR SCHEM_FTB        Buses created in Allegro-CM are deleted by netrev in traditional flow. Z# h) n% n- j6 V: F6 ?4 Z
1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.  k( S$ p. C* f$ ]
1048403 ALLEGRO_EDITOR SKILL            Allegro crashes opening more than 16 files with skill
: T2 a9 k0 b4 p& W2 {$ ?5 h+ ?1049262 ALLEGRO_EDITOR OTHER            APD and extracta crash owing to Wirebond.# w8 E- m# U8 T, b
1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
. J4 U9 H( l2 X. }1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.54 _0 D8 l6 u% o7 `+ H6 c' n/ P
1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
9 ]' r7 Q0 _( q; n1 H+ R1049956 ALLEGRO_EDITOR DATABASE         BUG:dbdoctor deletes fillets as design is migrated from old version
& F7 D5 a: l3 C* Q1050408 APD            DXF_IF           Symbol has 45 degrees rotation  in mcm but DXF doesn縯.
8 y: V$ O" y- G# j( n7 `9 f1 j1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
" S: }9 [# j% j% P+ j1050918 ALLEGRO_EDITOR MANUFACT         Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
0 e- C/ _0 z! g1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
. [  J) _$ \; d1 H5 A% L: t$ H: n1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1 ^( |2 N# a$ w# H1052045 ALLEGRO_EDITOR OTHER            Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3' g6 e4 p" u0 \  R% `
1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file; g4 C. v' |" ?+ s& k8 a- f
1052600 ALLEGRO_EDITOR SHAPE            Adding a specific cline causing shape errors5 P7 Q( f, I* {/ ?3 j0 N6 L9 ~' s
1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.! B+ f( C5 Y6 a5 B, C( P( V, p7 K/ C% D' r
1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.% [9 e. t+ ^, N+ {8 }
1054269 ALLEGRO_EDITOR MANUFACT         Backdrill Setup and Analysis crashes on attached design
& v8 i2 w* [0 b7 z: M0 a6 T- D1054351 ALLEGRO_EDITOR SHAPE            Shape voiding fails for board having diffpairs with arcs
7 Q- T9 m8 D2 C1054456 ALLEGRO_EDITOR MENTOR           mbs2lib incorrectly translates refdes label
. v% R& p. y% ^  Q- `8 [1055273 ALLEGRO_EDITOR INTERFACES       DXF exported from Allegro has an offset in pad location for Y- direction.5 l  O! I* y0 @
1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy! K+ s/ n9 H6 W
1055481 APD            SHAPE            keepout does not clear shape unless it's picked up and dropped down7 B% Y) p8 z, W/ g. t7 d
1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
. l# {4 w* T" o/ f$ ?. b- l1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
. `2 }; F' ]. h1056579 CAPTURE        OTHER            Ability to define custom variables for titleblocks that update for specific variant views8 d3 i3 U# b9 ^+ W- I& z& \, N
1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
$ ]7 f% Y. ^  t( m  ?, K1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
; T! H' E3 B' I9 ?8 d* q1058002 SIG_INTEGRITY  SIMULATION       Incorrect Xtalk sim netlist was created.
) `- J5 b3 R0 F9 G* C$ H& T% k& @/ V1058364 ALLEGRO_EDITOR SKILL            axlTransformObject() is moving refdes text when only symbol pin is selected for move* s+ A% ^0 @2 g/ b' O
1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value/ t5 [/ V0 A2 L: i4 ^/ {7 j
1059037 CIS            PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer4 b9 ?* ]& M3 }; F' L
1059389 ALLEGRO_EDITOR MANUFACT         about back drill analisys report
6 {9 C) b/ A: I* Q1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.% c+ c1 O. v0 R! B2 L6 J' T
1060428 ADW            DESIGN_INIT      ADW Flow Manager Copy Project fails to complete
& H: P' y. d, p" o6 `0 _# _, w1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
* h7 k9 A2 l6 q3 M/ y1060977 F2B            DESIGNSYNC       back annotate in 16.5 does not bring in already placed nets as global nets$ v2 O2 S* f; q. r
1061223 CONCEPT_HDL    CHECKPLUS        What determines a passthru pin?
5 n3 H' @5 @* }1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
, a* L# |8 z; \1061572 ALLEGRO_EDITOR INTERACTIV       Shortcut keys wont work after "Edit Text" command is finished.
: @3 h7 W. P* p$ `% C5 ]. }" Q0 \1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00- H2 ?" p+ ]6 v8 u
1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
: L5 P& p9 N; H5 l( @1062982 ALLEGRO_EDITOR MODULES          Module containg partitions has been imported to the main design and cant be refreshed.! u, o0 Y, _# P6 ?- R
1063284 PCB_LIBRARIAN  OTHER            PDV Save As is broken
; |* ~2 I, C3 ~& s( g- l" t1063658 ALLEGRO_EDITOR SCHEM_FTB        Allegro Import Logic does not remove library defined diffpairs9 o; d) x) i! x8 r+ P# w' Q+ T' F
1063778 CONCEPT_HDL    CHECKPLUS        The hasSynonyms CheckPlus predicate is not returning true for all global signals.$ t! w% h9 W5 }6 a: B
1063924 CONCEPT_HDL    CONSTRAINT_MGR   Highlight the net between DE-HDL 16.5 and Constraint Manager.
9 {, n; {" _# X( r1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design; Y, X0 \: ], Y/ r# {0 K1 n3 E
1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
# l& L# M) _, k2 G1065618 CONSTRAINT_MGR ANALYSIS         DRCs on board but Constraint Manager shows the columns as green.
1 z0 ~! a0 P+ A1 z' y; o9 N8 i" r1065641 PCB_LIBRARIAN  CORE             PDV symbol editor is crashing when deleting a group using delete or CTRL+X0 l+ W  k/ [. @9 J+ \9 _
1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application, I& D+ }+ {4 z* I
1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
  j1 M# j. L7 [6 `1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC! @4 X# p# K/ R  ]3 x1 V2 ?
1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
9 c3 Z- d* i/ b" m: K$ J1067339 CONSTRAINT_MGR ANALYSIS         Relative Propagation Delay analysis in the Partition file seems very inconsitent.
$ v1 m$ u" J- [* g! H3 n1 }& m1067984 SIP_LAYOUT     OTHER            layer compare batch fails with write protected file3 h4 C* w8 \" {8 ~. A! q1 s: \* ~
1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command
. B, x2 F; Y' S- g; ?! A3 l1068547 ALLEGRO_EDITOR EDIT_ETCH        Outward Fanout is not fanning out this 4 sided part as intended
1 o# O0 A( E" H( w: a" j. U2 T4 d1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067* w1 |0 a# `7 b2 d4 K8 }
1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
% c1 ]) _& P( J% j5 k) |1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify" W& H% y& @" E
1069915 ALLEGRO_EDITOR EDIT_ETCH        Allegro hangs with when doing spread between voids
' H/ i, w  d9 R6 n  `, l1070007 ALLEGRO_EDITOR PLOTTING         Export IPF omits drill figure characters for backdrill holes
0 V& l9 k( `3 j. n# q1071722 SIP_RF         DIEEXPORT        Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow, y" s$ w  V0 [  h+ q4 X
1072067 APD            EXTRACT          When expoting using Extracta oblong pads with anyangle are abnormal9 u! r; n8 E! e) r
1072791 ALLEGRO_EDITOR DATABASE         Database check cannot fix error and keep report the same issues cause artwork cannot export.
& ^+ C+ F( ?+ u& W/ m1072806 CIS            EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
+ Q: V, u* R+ j$ m4 U" j1072843 ALLEGRO_EDITOR PLACEMENT        The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
  N5 x9 z! J  E; g6 e4 a1072904 SIP_FLOW       SIP_LAYOUT       Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
4 r8 D+ [" q( F* a! r% Z2 n1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.+ ]; ]5 T0 J9 P
1073445 ALLEGRO_EDITOR GRAPHICS         'infinite cursor graphics fail -ghost copies as you move cursor
  U7 Q& P1 u9 H* N& B8 A9 `" R' l1073464 SCM            SCHGEN           Schgen never completes.
! s" k4 W8 y) p$ f8 ~1073587 SIP_LAYOUT     OTHER            axlSpreadsheetSetWorksheet command clears the cells in memory
6 g0 }  W! E0 `3 M9 r  q8 e! g) V8 ]1073745 CONCEPT_HDL    CORE             Import design fails7 X  L% p5 D: K/ g# l  V, n+ _  T
1073852 ALLEGRO_EDITOR INTERACTIV       While doing a Copy Via use the last 'Copy Origin'
/ S' h. R5 e7 w1074279 ADW            DSN_MIGRATION    Design Migration fails purge if there are cells with BODY_TYPE
  h0 u; f& R  O* y9 F1074791 CONCEPT_HDL    HDLDIRECT        User gets port exists in schematic but not on symbol message even though the port does not exist
" w, x9 ~7 H6 B8 _/ ^1075135 ALLEGRO_EDITOR DRAFTING         Ability to edit dimension text block in Instance Parameter1 v9 @  z+ t' h  e% d/ L! R
1075151 ALLEGRO_EDITOR SHAPE            Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
$ [3 f4 }$ z+ z2 e; D8 H/ _1075256 ALLEGRO_EDITOR OTHER            Import > IPF in 16.5 is dropping data.
+ x- a/ b  v" _* v! j7 ^& m' V1075853 ALLEGRO_EDITOR REPORTS          please add "PART_NAME" at Extract UI& ^, g# U( |, G% c0 \9 K' s
1075934 ALLEGRO_EDITOR DRAFTING         Able to Changing Dimension Text Block- I' n& X0 y) c0 p  C: ~  B
1075955 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer% E* h4 U* C5 B7 i4 B# W: Q
1075964 ALLEGRO_EDITOR SHAPE            Shape voiding is not consistent in conjunction with odd angle and arc traces% g  k2 Y# x* F- d9 ^' a
1076086 SIP_LAYOUT     IMPORT_DATA      missing wirebond after import SPD2
! `4 ^- J( T# |2 X1076202 ALLEGRO_EDITOR EDIT_ETCH        Allegro add connect causing crash after Hotfix7 ?: Z1 D9 X4 E; o
1076205 CAPTURE        PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
0 r9 s) q, T) X1076536 ALLEGRO_EDITOR DRC_CONSTR       Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top, \0 y" ]; }4 Q0 r8 B- Z
1076538 CONCEPT_HDL    CORE             Property visibility changes in attribute form not updated in schematic canvas.$ A/ D" q! ]: ?  H$ H" r7 m
1076655 APD            DXF_IF           Dxf does not get offset value if die symbol padstack has offset value
  g" W& T+ {1 d5 y, \1076846 ALLEGRO_EDITOR EDIT_ETCH        Grid snapping broken after slide in 16.6; Q, Z6 y& J  @9 @* I% N7 s
1076891 ALLEGRO_EDITOR INTERACTIV       Symbol rotation not displayed correctly when defined as a funckey
' q9 i  \- U- Z1 c+ c0 `( x' F& J/ z1076909 ALLEGRO_EDITOR DRC_CONSTR       Allegro crashes while placing modules from database2 D4 h0 r; v; j3 e
1077084 CAPTURE        NETGROUPS        Crash on selecting bus when Enable Global ITC is unset# R3 H9 o7 s& Q+ N9 q
1077169 APD            SHAPE            Shape > Check is producing bogus results.4 {: b7 N4 n8 y- j& R4 n
1077572 ALLEGRO_EDITOR DATABASE         Mechanical symbol created with 16.6 cannot be placed on board., v" r9 p5 D- e6 c4 a: T; x% s
1077879 ALLEGRO_EDITOR SKILL            Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
# Y% E4 h; X4 n0 A$ g8 E1078380 SCM            OTHER            Custom template works in Windows but not Linux1 b" K* e( `# [- T$ @1 O7 [
1078497 ALLEGRO_EDITOR INTERFACES       Import DXF does not seem to work correctly.
) r6 A4 D5 w" w; b+ ]5 ?$ ]1078682 ALLEGRO_EDITOR DRC_CONSTR       Unaccetable slowness with Slide
5 D! J1 K$ u% U( t4 O1079082 ALLEGRO_EDITOR PLACEMENT        Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
; K: i) T2 w  y) j* P) l1079533 ALLEGRO_EDITOR PLACEMENT        Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
. O' t0 a0 X1 ^5 f8 v! M1079937 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
* l% ~- t  c: P6 R0 N1082582 ALLEGRO_EDITOR GRAPHICS         Allegro hangs on a given testcase using the MMB zoom control
, {7 j: X( q  N2 h7 s0 q1082981 ALLEGRO_EDITOR SKILL            Allegro crash while change the new symbol type as mechanical.
3 P5 r' m- {! Z( |. k1 C& ~. s* T1083230 SIP_LAYOUT     SHAPE            Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.$ s& ^$ V2 Q# m  T1 f" P# T

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发表于 2012-12-17 21:16 | 只看该作者
看到了几个16.6的“特点“原来是BUG

点评

^_^ ^_^  发表于 2012-12-20 09:28

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发表于 2012-12-17 21:21 | 只看该作者
rx_78gp02a 发表于 2012-12-17 21:16   d/ S0 S( A: T
看到了几个16.6的“特点“原来是BUG

& e# U2 W9 o; F5 e+ U+ _4 l是的

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发表于 2012-12-17 21:24 | 只看该作者
有下载地址了吗?; p5 B9 V- ~5 A# f

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发表于 2012-12-17 23:48 | 只看该作者
Look & Thanks

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发表于 2012-12-18 05:32 | 只看该作者
本帖最后由 mengshang 于 2012-12-18 05:36 编辑 - V) M) m2 ~* V
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的确,Latest Release: 16.6-S001  p6 Y2 |8 o; p0 a! \
Your Version: 16.5-S034
+ ^  N7 _( r1 I6 r& c# q) y期待着下载呢

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发表于 2012-12-19 22:59 | 只看该作者
本帖最后由 micdot 于 2012-12-20 10:57 编辑
. V5 d4 q3 @1 O; X
5 K8 F5 {3 o+ P: E6 r现在提供下载地址:http://www.orcad.nl/patches/Hotfix_SPB16.60.001_wint_1of1.exe3 J( T  [4 Y2 l6 P' B
目前,我已经下载完毕,安装后确认可以正常使用!

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发表于 2012-12-19 23:13 | 只看该作者
第一个HOTFIX就有400多M,以后的会越来越大,这个怎么玩啊?
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