|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
6 F$ Z5 M9 J- f1 c* nDATE: 02-17-2012 HOTFIX VERSION: 016
/ Z+ d& g/ Z6 g3 T8 S, Y===================================================================================================================================
# y- K# @, R, lCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 W* D; _# g# E! G& r. k===================================================================================================================================
% x. m2 V- I) v840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
3 }8 ^# J; B' N+ f873075 PSPICE PROBE Decibel of FFT results are incorrect.
l) U# r2 @$ r938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
7 F% a8 M3 H3 l6 x' z5 D$ P943003 SCM REPORTS The dsreportgen command fails with network located project
0 _5 ]) ~" f4 I4 m961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command$ q4 ?. S. a, k) F9 w
962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
}, W% k2 w, O: A+ M962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend; j+ k V; c+ n1 G
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
+ x$ \ y9 e& K, w$ L$ w1 w& i968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.+ g: n% Y8 ]! M
969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes8 ?, p6 c, C& _$ x [8 }7 f
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~1 T( R8 C- B1 A( c& n4 m
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
7 t8 Y/ [# X* ?971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure) X, r. x& Z5 Z) F* Q0 z
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
' z, g/ ^) D0 R/ C973859 PSPICE ENCRYPTION Pspice crashes with encrypted model+ k' u+ [; w, y+ m, M
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing4 q% e: [2 n8 v0 N- Y: T( t
974540 CONCEPT_HDL CORE Graphics updates are real slow" i* l% B0 T* \ N9 w$ H; y" q
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
" `6 O! Q" R) _$ Q' N( ]974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
% j* t& h: Z e# O" P0 e974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working/ h9 {- B, P% V9 U2 l
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
" H) i1 W- D9 E975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5$ L$ j, T, l- }
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)) D8 g. f0 d$ n5 Z) b5 \& {: k
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
9 d& R+ C, B' t6 b( e975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
4 V: F, F B' [$ U. w1 U# Z976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.4 R% t/ F* r/ N5 Z" Z
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views0 @- ^2 s1 K h C/ h
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design! Z) g6 E% {& @5 `- y. T& T
976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design I. P7 q$ D% }! r- m" m9 j- M% g+ p5 u
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC% ~0 M& n0 P( ?% D/ y
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
4 J; w$ V) V& i) R% d6 U976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
c! I I# |# p976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models. w3 A& M" i' N& D
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
' [ q. l% s+ ?. @' i977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
. \9 L! S8 O- O: y978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.
7 k3 u! J* u2 u! Y! s978744 APD DEGASSING Some shapes will not DeGas on this design
6 I3 N9 ]+ G0 r979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
* Z2 _3 Y- O' Z d! @981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
8 D0 m: N% [& q9 \+ k; Z1 U; k! Y( z' f3 E
( J7 T! \' o1 K% f$ ~DATE: 02-03-2012 HOTFIX VERSION: 015
) }& a% p, i q6 h% V: k===================================================================================================================================5 S/ n' C2 Q9 D5 g: I0 |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
. E) s$ f$ G' s& S7 N===================================================================================================================================
; Z$ P9 Q' E& r871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager2 u; v3 {7 j% i7 q" H, g
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
) K8 t: A* C/ G( Y8 Z$ A941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design7 d- `5 a3 w" s4 }2 L* j% k
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning3 l* l, B4 h8 W/ ~) g) q1 N
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version3 ]+ o0 ~& o3 A
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project! V5 E8 o! H5 h' u1 T
967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
; k5 N; w# ^7 f7 K7 E" B4 d968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol4 E% }( m, Y1 D: D0 A
969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
+ x+ g3 K7 ~0 T. C# v1 f8 ]: N970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
9 B# @4 B; ]& f7 C5 M/ J1 P970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins$ Y, @: g$ ~* C' M! F" B
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.8 L$ V) i; `% y
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
7 n6 q3 ~0 R" | \ Z970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash* T: |2 A7 s5 d. x& H. |
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design: v/ P7 M3 f% o7 ~
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
; \+ K( p& i8 f5 T$ K9 B; h972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM% ~7 i S6 j1 E x( m3 `) C
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT
. i8 O2 i6 W6 R) y973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.$ B# X- H3 E* N Q. D. x
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized: P. v3 x% x( ~
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
/ A6 X$ H* H5 n f973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.: }7 C3 Y& M/ e. {
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net, R- [2 {$ B# F
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application- P( P* }8 n2 c. n- p' N. M* H6 g
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.% y1 q9 _" ~( x
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
. e: Y& t+ m B+ l' O! n1 _976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
1 H$ e/ c3 p' x
0 L6 p) x3 F8 x7 ]DATE: 01-20-2012 HOTFIX VERSION: 014. [/ g# e/ Y% f
===================================================================================================================================
" r' k* Z7 `! ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
; X) S5 X* [: F& A===================================================================================================================================
6 i g1 X" J$ p8 ~* ?733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
) D- J* \0 \- ]1 k7 R: c941020 SIP_LAYOUT OTHER Soldermask enhancement
; q, N* ^ Z6 s4 A946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
+ P# R6 M" [/ H9 l. e953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable6 r( r/ `+ b8 c: `# t
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
9 t3 G- w- Q1 d) M+ y* `- r& |; d( _956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs
2 ~ [" P2 _6 h; [5 E: E958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
: ^1 s6 @9 s- _# k. U/ M958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
. ~- H- y( Z8 @' m; t959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.4 p, F" _: e/ W% Z
959940 APD AUTOVOID Void all command gets result as no voids being generated.8 U; O- y2 W8 w* i: Y0 B" L8 H
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
* m7 f1 {% @% x. r961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
- X" f/ r- s) |1 w, g2 I$ P% x961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
4 K, p7 q, t" x3 N, s( c, Z7 L961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
! N/ z2 O% G D* M5 O961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.3 n8 y H/ m5 D% Q
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
2 e7 U g& x- @4 \961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
$ S+ E% b( }6 N6 z& F$ n962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
$ J7 g( y0 v2 n1 \; Y( h! P7 B, a962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires, O. U1 H% g/ d; g A* s
963232 CAPTURE MACRO Macros not being played in Windows7" K, n- D& i& v- X. Q
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.32 N4 ~' P* K' b2 C1 [2 f- x& |' _3 i
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux
, r5 }' e9 b* z5 a4 \' _3 f; c963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
& G7 F' o7 X3 W+ E! h! b0 P963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length9 k! J! J, Z. v G
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym.../ e' B# I6 \7 T# @: M
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
* k8 P2 A9 D4 p9 _7 d1 e9 u964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)8 f7 P% a' L& L6 o
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import. j3 @) b: O1 d9 d4 H' j5 z* F
966416 F2B PACKAGERXL Cannot package this design
! S- Z+ p# R2 [( F* w$ w6 C966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks y0 \( ]/ u7 t, e" i
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
/ S1 [8 [( u; X! _966795 ADW ROLLBACK rollback utility does not honor -product option from command line
/ t3 Q4 s* R0 u# _- w/ e$ x967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
c; f' Q. F4 ` l) I, G! R967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
6 z5 i$ p! ]- q; T' P" y2 w967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
; t. N8 M& U, t6 u0 i: U3 r) F967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.) }+ [- f# _- ]" r! _. U2 _
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL/ M& E" K$ T* b% O: A8 Z
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
, w: D6 r8 p$ r9 J R: S968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
3 b# g% H( _: a( V6 \9 Z% s( \968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
+ p# ]7 C$ s8 @/ X969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes( [) }, B+ y- W
" u! P6 E1 F; A0 C/ WDATE: 12-16-2011 HOTFIX VERSION: 0130 C7 Y' j J0 P x5 {6 a( p+ D
===================================================================================================================================) m% P4 B# h4 C+ s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; [5 Y1 B4 U4 O5 W% e" n1 d===================================================================================================================================- t q3 ~/ @8 @% V; R$ R
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
: D* G/ O5 D( T8 s) o927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
g- ^$ r0 K3 H: Y5 h' w938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
/ V! L3 r X. \' ]941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
$ p! s' S0 `4 f945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
) X# ~( b Y2 h0 C) L3 M/ Y" E, b946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat' f. n& a( | D! @3 p. |0 S
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.7 \7 ?5 |% K8 V- g
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
k. `, w# N5 i s7 ^953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.9 G2 M A+ }( J) n* k7 i
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
; }( ]" k! q3 k2 T953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly1 P, O1 {: \, Q8 X
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
8 \! w" P) d' o5 b954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.$ t E8 `( ]8 u2 e. B2 Y7 s# M
954498 SCM B2F SCM crashes when importing physical
* i! ~% S* U& M6 B% [954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
9 r& i4 _' x0 H3 G954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.34 m, V; e0 N% Z& V+ _
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
' i7 F% D3 w" }, o7 ?955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
, `0 s/ J) u6 }% h: A955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window1 |+ E+ u* T+ n1 H. h
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S0391 e$ ~, J6 ]: f- N* g
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
8 K) c% k6 \9 L/ T1 h955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL: d4 h. R, r, J
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
: x/ N: E9 B) ~955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass4 a; K) S: X0 [
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void( t$ R1 g) T/ y$ j, ?9 r x1 i
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.2 b- K7 x# _0 s4 x, n: t
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
9 A% y0 q: \1 R$ `4 o3 P% ^3 Y. }( q956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
+ E0 w; R3 `" o6 D956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found; ^0 J2 Y8 j" V4 b9 c
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined8 s) ?: u3 f" D8 y9 q* n |8 ?
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board; ~6 w" J2 k& N j7 u$ t
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component4 F& L/ ^6 j- W7 `# X) s
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly2 a$ z! U% y3 b/ z# |8 A' V
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
O) @& u& ~) n956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
1 H- ?- [6 b/ [( R# D956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
: T8 N! o. T8 ^% s5 d" _+ R957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
2 j6 S8 E6 d: ^ `# U! X! ~957137 APD DXF_IF DXF out command dose not work correctly.
1 F U0 H0 Q6 ]( S$ P# W9 |957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
0 f+ _; V& g$ u957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
( s4 s9 Q1 A8 m7 s2 b7 u957267 CONCEPT_HDL INFRA Packager Error after Import Design' k4 m5 C U# O3 d3 ]) o; [
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file" t. f* I2 `$ ], O6 r: b" j% ?
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
1 }8 |3 `! n5 \4 |# K958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
6 j6 y6 h) z- b" L. W( F: n958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
% i1 q# c2 z. [2 r958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs" e; c/ Z+ q; |. Z' e* T$ L& E
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
+ m0 D8 r7 ]* @$ R959011 ALLEGRO_EDITOR OTHER copy problem of via and cline7 h) N* Q+ |- ~% S
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs! C& t/ A0 ~! n3 y% g
959253 CONCEPT_HDL INFRA Design will not open' `0 G: B, D( i7 X m
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
4 P4 j7 j8 e. m0 g" `) z' |8 \959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.5 ?- Z# J6 ]% L
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred5 u6 R0 h" f( E+ `9 [9 [2 m
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.5 l; q& G, X9 @ ]+ X
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
- D$ M0 P1 e& o" K+ i: B" E# r960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter0 q/ v* u" ?+ C2 W
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3$ g, |! C# ^9 U* h9 V3 I
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
% T4 Y& n- @, e9 R9 ~0 \962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
5 r: _ {9 c( w W. ~ B3 j" B$ v5 }6 E, l
DATE: 11-30-2011 HOTFIX VERSION: 012+ _; V: g' q h( m
===================================================================================================================================
/ _2 c: H; `7 J+ bCCRID PRODUCT PRODUCTLEVEL2 TITLE+ N; H9 Z2 A+ J# S4 m2 c$ g& {
===================================================================================================================================5 U# {0 f/ P. d4 c
959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
7 d7 }3 m. k3 H6 _0 [# x5 b$ {1 K% k3 Z, |+ u# M1 t
DATE: 11-18-2011 HOTFIX VERSION: 011
* Y) [! k5 c. J3 C3 A5 g) [===================================================================================================================================7 ?+ B4 E$ H6 B n
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 u m7 d, {1 R5 j0 u
===================================================================================================================================. ?5 b7 Y+ i3 m+ F( n. Z: c
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape4 f0 R& P7 a/ O) N
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?; G U O* g" z1 j! y' j
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
! e7 m$ H# k+ ?909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
0 `+ \! R8 R) T911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design., D% L& X+ a& b! j' z* Y
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
* x) G+ S5 b5 m. S, P* l921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
) J5 i5 B h# c# N: ~925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
# C, j( }) Q5 Q5 d& X926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows: n2 G0 Q3 |+ y0 Z: l/ y* [
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
8 S) O5 }7 A2 ?934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.9 J! i+ o. I5 S- n: L6 v% ^
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
. t% f* _ h% b' X937165 SCM SCHGEN Can't generate Schematic
M0 ?. S+ b6 }0 c937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search) c( W2 E) @" e
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
0 m& ?$ M1 Z$ S7 z939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
% j7 ]7 U7 a- m6 X940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup. [7 ~! A9 U# f H
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in$ n/ D! W3 q* s* ]( g; O0 f
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad& Y# t8 m6 ]6 k x& T
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.. _; f2 f8 t+ J. c. {
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
- g! {& K6 S, \) e0 i% v941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups" n6 v+ o w1 A. k
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.: u9 D5 b% E! C+ r7 |6 H, h( |* N
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
`8 [& ?& `: a- i, s0 m941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?
N; j x( Y F |942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture# c; G- J: P; B# K4 I& t
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel, ~1 d+ s( O7 k2 J3 V2 E6 ` b
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
J6 Y% Q4 ]6 b, P% I: f942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
1 U3 V6 F- r5 d- X8 n$ n942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.$ n, R+ K1 m8 }! ~& a+ V* Z9 H
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
1 u! O2 E0 D% Q# f943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
! X6 a; r2 `0 T943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup5 _0 [4 X5 \/ ]: w' e8 |! K! F
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
8 h/ S% H, W5 |' {944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
' `$ [+ ^ O. H# ]. S! N944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines( ?6 k. P) G5 K* n- f
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints2 M- V. G+ }8 `. S0 Y$ [. _
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
V& D3 V3 Q/ g) ]6 e3 H2 x' s946350 F2B DESIGNVARI Variant Editor rename function removes all components' N( @2 V. P1 F6 Q. y+ Z) y' G
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?
# i+ _+ ^' g6 y- K# ^. ^7 u" ?946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form7 ^# l6 w# E' r* R% c
946458 SCM SCHGEN Schematic generator adding an unnecessary page. q# {; E; R) j: g6 q- F3 X
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
* {- o, E$ L$ O947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
9 H& K" p( u( f: a3 Z" o! E/ d948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM- n; Z, m2 w: u. [. O( T
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.
# x% @3 p) L6 _& g4 ^" n- G951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
7 P; F3 k* {% I- k951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original) L+ I: H" X3 l
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?2 _9 c" h$ ~7 i6 o; |4 C: e7 \ \
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages4 l& _* W; }5 _% a* U
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
. y* l2 I6 Q6 V952057 SCM PACKAGER Export Physical does not works correctly from SCM
4 t( d# K3 o$ K& P952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor. N) P: a, E! z( p, N0 d) U- M4 i
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5# `! @6 n$ q! A) s+ D3 |1 R" V
953018 APD REPORTS Shape affects Package Report result.
! N$ a0 ~" I, [7 I- ^$ q1 X953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.; b! q/ a6 `7 y/ e
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro, B7 |" s) ?- Q! y+ ?! \; }
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
; f4 x7 |4 E! u, B }$ V- K+ ?! U954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
( z: O8 t2 C( @# i3 s954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report. ]0 ?- X% y" N: p% y3 }
/ \4 t( N6 m5 M* n. L0 V" _DATE: 11-7-2011 HOTFIX VERSION: 010$ Z* D( C5 z5 o, p5 d) `
===================================================================================================================================
4 u. k- \8 X4 {2 NCCRID PRODUCT PRODUCTLEVEL2 TITLE" B' E/ ?8 V! o) L# a
===================================================================================================================================
0 X/ Z% Q" A" w2 M q* x658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
- l' L6 Y Y j) Y+ u928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
' n# W6 t- R+ r934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile# r/ D% p" W7 b( W$ E
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem5 v0 P7 x2 D: B' @
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
# w) S9 P& v8 G/ A# R938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
9 D- F2 B1 n1 [3 J u940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
( {7 A7 O, W1 f; t) @941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!7 W4 @/ k& S" P8 K: m+ {
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning
0 Y9 u2 Z) G) B+ \8 @. ~941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
, r/ k$ `% o0 D, P) ~4 }4 F! u942914 SIG_INTEGRITY OTHER ZAxis delay calculation
S6 h- O( i" N3 j* b! I, {) a943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
, J" p' @6 s+ M, V, t2 n945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
D0 n! w" g' S8 H945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.9 a4 Y3 T$ f* k& v: X$ l$ S5 e7 D
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection." n& ?4 S2 j, n6 P
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
3 j% ] [; t; _* j3 Q* R946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
# F3 w) z9 q6 O! V2 m0 {! h946819 SIP_LAYOUT DEGASSING Shape degass command! O' m W, r( O& G/ a# S
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up7 r4 f, d3 k( b# X0 T
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
: m, C5 j1 h! W7 a% e947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file$ V# B/ _6 e. m2 W
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic+ `- S. e1 p9 u
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
6 j2 v% h/ s( P* a! O$ ]# J951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
! m3 V8 }4 q# P/ i! O4 Q6 G" }# n+ h: s3 F
DATE: 10-26-2011 HOTFIX VERSION: 009+ e' ]& Q$ I6 U8 b7 a
===================================================================================================================================
/ D+ T" n! I7 R+ y' U# UCCRID PRODUCT PRODUCTLEVEL2 TITLE. p" |0 x, ?( o! q' f
===================================================================================================================================
1 a& U3 e9 y# h% [/ g945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet. Y6 [4 `! M" B
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
' U# a& R9 \# \$ e( u
# h: u9 a+ N. R6 lDATE: 10-21-2011 HOTFIX VERSION: 008
6 S# z( y+ ?1 m* M- U# o+ G===================================================================================================================================
; [4 F! _; q% L! T# E# yCCRID PRODUCT PRODUCTLEVEL2 TITLE/ U! z% ~0 r9 @* y6 z! y7 {( W9 F4 Q
===================================================================================================================================5 R! ~7 W- V6 `* n
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.7 T" l8 N! h: x3 e. H# M
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.57 r- S" J; ]. S' l
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it# f0 I6 T* F) l0 @9 c" C
929348 F2B BOM Warning 007: Invalid output file path name& _. z i- a( ]
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
( H: k$ `, R4 @( ]9 Y930783 CONCEPT_HDL CORE Painting with groups with default colors: u9 M8 X6 V) M
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.. B; `. Q8 X" G2 \: O! s: `
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
3 v6 s- W6 G/ G% w B938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins* }" P& F9 [* b8 E
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
8 [5 \' y& ~$ f/ w, Z2 g) ^: X* M939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window4 F& w! X& {: w! P
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
- [7 @" D$ T- @, x @- U' z939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)8 K/ W" Y8 C/ h, q$ E! a; W* D7 T2 i! y
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set. J: i8 k( u( }+ i/ ]0 D/ X
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.& r: Y2 |1 @# ^0 G' _
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash./ G( f: b% ~: a! q6 P
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
) Q8 K7 Z+ Y+ _& J! f6 }( d940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
8 u+ N/ v3 D. h5 V941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks' d, L2 k; J8 g% y' A( _; d
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
; D' c( i& a, ^$ m942210 SCM OTHER Is the Project File argument is being correctly passed?/ U4 L' J7 \( K* m
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
! ?5 e& L! C9 ]0 {- U0 w5 P) Q942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
: L1 i# L+ i7 F& b' j1 Z) J# ^$ j943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash7 n2 y. K8 S' q' W
# R" o, k8 q5 V- m EDATE: 10-21-2011 HOTFIX VERSION: 007
, n$ _2 }7 A$ F+ ]1 E0 h- d$ h" j===================================================================================================================================0 [9 U" O1 J, H5 F
CCRID PRODUCT PRODUCTLEVEL2 TITLE+ E( N/ J) p/ z3 e+ M" R+ G
===================================================================================================================================+ R7 Q0 H1 f* S/ C8 b# z1 K
841096 APD WIREBOND Function required which to check wire not in die pad center.- L( A" `- s6 Y7 C8 B
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
1 y L3 S# x D4 b& h4 \5 X, `906692 ADW LRM LRM window is always in front when opening a project. R3 R; @ K: J- V6 r
912942 APD WIREBOND constraint driven wire bonding
, Y! D. [' v& e2 Z912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
0 e* X" k% H% p4 V# \# e915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design z: @$ i" G) {' i) B2 _
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors. x/ p% X9 P' m7 U3 Y% Z6 G# s
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
" m4 M: _/ G! \0 D D/ S; S; o927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
. ~) U3 | R/ I0 R/ D927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
' E: r3 m/ n" r, l930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one8 }: I; e& g I" n4 q/ E
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation8 Z0 K$ y' _* j7 o2 O* p; g
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked./ F! |2 {. I8 o: P
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?9 V; S9 u0 K; {8 |& w+ x
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
4 m8 Z1 K% l' S" g% j930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form: r" _: v v* Z# S k' F
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
! h+ Y# E$ I4 m8 @. y932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
; D5 F, G. A" z! r2 m932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
. O% M; h# h n; ~; j932292 ADW LRM LRM crashes during Update operation on a customer design
$ T5 e; E- h' p" v$ C7 V932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
7 n* q" S/ |/ q" B4 s/ O7 J n( p932704 APD DEGASSING Shape > Degass never finishes on large GND plane
% [, V+ v7 R% j! h& @; v9 w932871 APD GRAPHICS could not see cursor as infinite
4 Q5 q) L2 Y: g932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
) v/ ]5 l! v7 @8 J! n8 k4 G0 j. L932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #054 \0 a# j8 o! [, R: H" l$ k
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members) r$ K8 m( Y4 O( S. i. K k) z
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
: a& L4 w2 T% t7 Y3 N933214 APD ARTWORK Film area report is larger when fillets are removed" t/ c1 v1 Q/ c
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
; q6 _. |- u2 ~) d, B7 ]+ ?933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
3 x5 A- `$ }/ i5 Q933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
; C) f1 h# k' f" {934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values& R6 l! v) O$ @! b
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
7 J; l. D# K) C" @% x( \934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash' O, ^; Z$ i/ x* G _+ M7 X2 Y7 F/ I
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.+ }0 o5 f& c, A, c) f
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
: }' U3 k# G: r" g$ L5 j934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound3 F1 o( G* |1 w2 J1 `# q/ l
934909 SCM UI Require support for running script on loading a design in SCM. \. y1 y. F$ c: k
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
* e6 x" P% N1 Q) F0 j3 y935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.33 l L5 P9 [ ]$ u( c' F2 N0 ~
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
3 ?: `( I# O g: n2 r, z" c" p& P936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol' \ K& m$ {; D1 ]5 n0 G
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.& c2 d+ U" Y. s( O* K
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack7 u6 X0 Y+ T L* A* C
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
5 D$ f J; g+ H936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol" Z/ h' f! Z! t3 X0 b) b
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
* J; p9 h$ E f$ S937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
! T" K* O; P3 k' o' d937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
; t$ J+ c$ W# g: `. R! F" u* v$ e% r937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
3 H! ]* B0 q- ~6 D, Z% D937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.8 |0 v0 J- p2 e8 Z. G
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
# @4 R$ E; `$ i7 B! Z x. x6 a7 F j938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
5 p) T/ X" i: [! W
" n" u2 I, V0 I* @6 e6 g/ z5 rDATE: 09-16-2011 HOTFIX VERSION: 006
$ `$ [# ^; z& P. X; j! ?===================================================================================================================================9 h! O+ E& j; L& o
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! b9 H) A5 `( t- n" e2 p===================================================================================================================================& D' A. A+ S# i+ O1 C! L) d$ b
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.6 `5 q# U* t) E3 B' ]3 G
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
4 ?; H% ^6 L% n! Q |) j919822 TDA CORE Cannot configure LDAP to only list the login name
p. J% _+ ^3 s9 y+ `7 {6 @9 b1 c" ^922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
9 n* v( K+ `6 F' G924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
6 v5 [% {0 B, B; i: j) X9 u, d; I924448 F2B DESIGNVARI Design does not complete variant annotation2 I- @# w5 Y9 l$ u, C
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB( q4 Q; E* l% |) Q# d8 v0 S1 c, `
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
: \$ u$ o+ S% r! B* O }8 Q4 I927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
; ~& l/ j& h! @. g; }( ^927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
1 D- ? N& a9 D* |5 H: f927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
: |2 ^% o- }$ e4 [, {927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
( N2 M- Y, c7 d. x$ C4 A* \* p927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
# ?# `( K J- u927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display; }( s# O$ W# y0 r
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database2 {2 m! M4 t: a; J
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
% V1 F5 F2 f- P4 B& r928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
6 q3 `( Z% |+ i; a4 ~3 l928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
; \# Q' j0 X7 D/ z$ `2 t928738 PSPICE PROBE Y-axis grid settings for multiple plots
/ F' A* ~+ ?: I( ]9 c928748 PSPICE PROBE Cursor width settings not saved
6 c. @5 ]5 f. e- m: N928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
- G0 F$ W2 l! Q& J928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
) z6 `! C& J! `, p ~5 J% `928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe" ]0 z+ ?, @1 |: u7 \, a' c' }& v+ C
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
) y0 s! X4 G; _929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP3 ?5 x+ O% J4 \$ |- V* z% y9 H+ F
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
5 `( w0 K6 q+ u s' W' k4 [0 R930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape6 Q3 P( I! ?: D0 H* H- Q+ u
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
. m0 U" a6 y3 F930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
' d4 p9 x1 H& j- ~0 r930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
; v0 E: x& S6 I930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well+ o1 A! G8 ]4 V
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
# O& M. u6 \* ^" S- g930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked! s7 Y/ e0 C$ q/ ? C4 a( |* k
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens N- ~4 ~3 m5 R) `9 X8 t4 D" d9 w
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
, P8 o2 E1 _* u+ L931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
' m! ?% L h7 \0 M4 C' }8 y931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.! N* H- W+ O2 D
0 {; d% K- F% q8 M3 a- s vDATE: 08-31-2011 HOTFIX VERSION: 0052 L! b# D+ I& M- y0 U
===================================================================================================================================& U' I' C5 g* ]# B; i! F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 R5 I X. X. \+ L1 ~8 a) ?===================================================================================================================================
) p! h+ \% I7 E3 l825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole: \% d+ C! u/ y" J3 Z
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
8 \% z6 f$ Y% }7 P" m; a891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
. R: V; ?; v$ a910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.- g) r; w' X9 l u7 }
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.$ t5 E0 J' M: b7 l) s: c: O% O
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs" A1 C4 H5 A S/ f+ g5 M( F! ^* u
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
% {/ i- \; d# g7 x/ r915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location1 o1 e9 \( y. @/ t. ^! o j* F- e, g2 {
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape( ]/ R3 M6 j' }% A9 q' a5 L
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
0 j, W) Z- E% o- L, G5 D916321 CAPTURE GEN_BOM letter limitation in include file
+ X) [8 b5 a0 t& Q916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects2 m) @) ^# h4 L; I
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.: y7 \2 z! q. G
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
/ W m& ]/ N. I7 |) G( O/ n921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set3 y- p3 t8 w$ S+ Q
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.8 R3 I+ N* ]: N
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
: ~& ?8 e$ u R921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
; }! {7 w" }3 k. w2 L921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly5 `" P0 ^- L! K4 ]( ?
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.& Y& b. t; ^) A/ {
922117 PSPICE PROBE Label colors are not correct in Probe
" L' z0 n! I" ~! f% t0 V: s1 K: X* u922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
" T$ c8 k5 u$ l2 w8 V' k- V923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
: O: b1 c& W2 t923286 CAPTURE DRC DRC markers not reported for undefined RefDes" F( n; q) W3 `2 j j, B
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.50 a* X- W7 m: m" Q
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top e$ w! p ~, @2 P- V8 l1 m% b
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)* x {/ C0 h8 ?. t i' T2 H+ S2 n q
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
2 @% R" ^4 F6 w923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design% ^+ g* F1 a. t0 C
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on4 {7 k- P' ?2 ]2 `/ G) u
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error- b7 O# o- A) ~1 v, Y) E
924458 SCM OTHER Project > Export > Schematics crashes
% E1 w Z9 z/ L. y" T6 X _& {" O924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
+ n, T: e* Z* j: r2 ~925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect5 Y U3 q% g0 C9 ]5 S; {5 |
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
1 d8 }* M$ _8 L( ]1 b/ Z; ?/ ~925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
6 c2 E, N' A3 n: Z* N925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
1 i) d) R, B( g' I3 z: _925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?) a: B$ f9 ?' c: M4 c* j
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS q$ U$ ~6 Y! p0 Y/ ?/ s: \7 j
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
8 ]' U/ S w& r2 w6 O1 s2 k# f8 L926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed./ u9 I- R# X0 v: Q! F; h1 Z7 P9 o
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.: ]4 m6 R- ]! F/ B# [) d7 l, A) B
926503 CAPTURE GENERAL Memory leak Capture/Pspice
. N" q3 ^* B: d7 l8 o' p; r926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet, U: j* x+ z" `( V" E+ ?
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
7 l5 E r& p) u926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical4 u" f" Z8 f; U/ p% x& S0 E! p
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
, a* M4 s/ T2 W
" R3 O$ N- S, D: c$ gDATE: 08-19-2011 HOTFIX VERSION: 004- O# u I+ u! {9 Y
===================================================================================================================================
. K) ?' W+ G- [! jCCRID PRODUCT PRODUCTLEVEL2 TITLE
# @( \0 ?4 Z' n7 u; j, {/ l===================================================================================================================================
5 f& d7 Y `, |. ?785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
# X; G" D B# N/ [851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.9 E( b+ D9 P, x/ d, o: J
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
8 ^6 G' V0 E! u( p4 A) k870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file/ n$ j' _* h) Y9 ^, S' x
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form- V1 W% a3 _* F' q$ O9 m
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
- _" {1 K9 ?8 \# }895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
, N5 B7 L u1 C- L9 f895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement; P* A6 S: t5 ?: k& C5 o
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.! ? D/ Q% g* V0 X w
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.6 _# F8 [+ K0 Z; \
909469 SCM TABLE ASA crashes when opening project
/ u- N j! T( u& o909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
1 G2 ]5 H+ l) c) `5 ^% B& D911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-1528 ?3 b. z/ I4 V0 A( s2 D$ Q; o
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?) l3 ~- X7 a4 b/ I! p9 Y* X" T
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability* w( I& r7 B: s w7 Z
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP6 {: w9 Z O$ x( b2 k; s
916062 CAPTURE GENERAL Auto Wire Crashes Capture" Z y: {+ D4 [
916820 F2B OTHER RF create netlist with problem- X7 w7 w7 n! y* \2 H
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
* X+ p( W( _7 r5 l$ }7 M3 l" ^919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
! g7 r3 K1 @. Q4 e2 o$ m8 g919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working: ^8 z1 |9 _% f I/ O) B
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL( q3 r: J! k. {% P0 \% a' V p
919976 APD DATABASE Update Padstack to design crashed APD.
$ t/ u5 W: y- ^1 k- V920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition# }7 q. J( f4 U3 R+ b+ W+ u# V
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
* ^, w5 R. j& B: d {; K3 i3 i4 l920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
: t- }2 s/ | x/ ]6 y/ J5 m920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins& u' E9 m7 ?5 h1 N
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
& B g( w% B! V- M920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
& P5 b1 w. P2 J5 ~921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
: I! M M% L8 ]( J/ j# i922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets% Y ]' g8 [3 `2 ^. V
922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
6 d7 D; J5 J9 w6 ~922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin9 U) Y) `8 d/ V
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.% l3 L: @7 H. s6 F C5 v
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.2 N$ _( P) t- r5 v
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf
/ R$ z5 Q' ^9 g* J
6 P0 F: _+ O0 K7 c# Y5 cDATE: 08-4-2011 HOTFIX VERSION: 003* M6 O) W: U- m2 `2 k, v
===================================================================================================================================
M7 k v7 v+ |' p% t$ ZCCRID PRODUCT PRODUCTLEVEL2 TITLE. |! U* G) `+ X$ P7 W/ x
===================================================================================================================================
, f6 j6 J0 A7 [! H787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet., t6 l' a" y$ ?$ O
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics, t3 J! N h' Y P) \- m0 {
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
2 S# z% e/ U3 V904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
- \! C x9 r3 T- d( k6 Q1 |905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged8 x7 Z8 k/ [7 F3 M! y' j7 |4 M
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
8 u: @( o3 [. r. M908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance2 h) N# K# s3 ]9 i3 Q
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.
# V# N9 j% Y4 i" C, C7 ~910315 ADW LRM Import Design with ADW causes partmgr and pxl errors6 R+ k/ a( }0 v3 {8 \" ?3 Z
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5# z: y1 y0 ]# S
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5. L# @% b5 J( D3 ?( W5 A
912343 APD OTHER APD crash on trying to modify the padstack& s M9 f6 P D* ]2 C6 }
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
2 R4 A4 ^6 p' B4 E" F7 `( ]912853 APD OTHER Fillets lost when open in 16.3.
8 p, {+ W) L: z7 A0 g' f- R3 u913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
0 c3 j' _# R. `) @) C( Z914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
h# S, v, K0 u4 e914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
; B* g c/ g1 X( l' r# u! c914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
2 ~& T! u" Y; ]914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
- u# q' @0 c: S: z4 ]914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape/ ^2 ^* E B4 P- u: L# }. _9 E
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
2 ?+ @. ]- ?+ U914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
0 {# s# F+ [- J! b. M- ]914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.# G. c& g2 \% g$ d/ `
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling( c3 W/ E9 l0 G; d$ `
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3. s4 I' }' L6 `4 H
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
# K, _+ Q( W1 j- \' y f4 Q915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
/ C$ ~+ @! F$ Q4 h: |% j916154 SCM NETLISTER scm crashes when exporting physical database to allegro1 w3 }9 S( |- N0 |* d4 J5 {
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors7 M1 A" z6 z* ]3 }- W
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor% B' P# t: ^5 i7 [1 u- d
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report9 o9 V; {- _9 K5 d9 S6 l4 \6 s
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer+ b5 Q6 X+ G* A
916889 CAPTURE NETGROUPS How to change unnamed net group name?% n' l6 W1 e# a( f
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film8 p( {+ |3 t+ b: f, u: s
917434 APD OTHER Stream out GDSII has more pads in output data.
3 X u+ I8 ]# t& p; y! U& J7 e, C917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net9 u$ U+ x) H( I9 P7 m
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.- e; C% ^4 s( J' F5 h8 u, N
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
4 l9 Y3 Z% n! q# _1 M) Y7 N& f; Z/ t$ a1 p+ ?
DATE: 07-24-2011 HOTFIX VERSION: 002
: }5 \, _* \$ T% n===================================================================================================================================
, [, x: _5 |3 G. x2 m, [CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ }! X' w" A0 H1 w' E===================================================================================================================================
! J2 C0 g# ~5 J, O1 N527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings! L. i& q! V5 e( z) K: h
583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
4 U9 G- }: F# B" \( F1 ]! Q# M592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.3 n% s) ~9 g2 D
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
9 l+ n3 S3 O; z: ~ v+ y# u% i' h773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
( w' s( ^ M) B, m/ Q774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
* }4 q7 Y# Z' }( r, |: e799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs4 l- z# c7 x0 l d' W
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".& t w/ D5 m6 i8 Y( d
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
. x% {+ z$ K" Z) Q0 z8 ^821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format1 c$ U6 f& G7 b3 B' |2 ]
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
! o: \* O' V" n# \1 ^! @2 t0 G842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.4 Q G1 Z& ]8 |- ]5 H+ l* B
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
$ ?( e: }# ?9 o, K860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser* }1 ?7 u% ]& c! h9 [
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
/ `; a) l* j% [: o* V/ Y868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
4 l, m8 [8 ~2 N1 I882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE$ o) n2 B: M. r6 p* y
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
J; x5 K; Q$ R6 Y! O893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.2 S& y# ~; V; f. [! a+ m" l
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.' N1 d/ u1 g) S" ]3 ?* x8 t
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
8 U, U2 Q1 ]( H, Q9 H895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
' N' _! N# L% A, Z5 v896598 ALLEGRO_EDITOR PLACEMENT error message is misleading5 C& Y0 ~- G% `3 B5 j
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library1 l1 D) @ q% V
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.8 t% u8 C% w8 N
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
" L! H) Q! ~, k: s% h" F' f900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5 `) {' p3 }: p( v
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
. k/ k" v2 M$ ^) k* U w901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
/ Y7 l- g( o1 a* X! u) q902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains8 k, H9 V8 E* l
902349 CAPTURE LIBRARY Capture crashes while closing library1 ?5 L, m9 a) R' S, E( m
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
" R: h" N/ Z* y* X902841 CAPTURE GENERAL Capture Start page does not show2 f. t ?+ p8 A0 t, R; t/ N, p/ t
902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
' p& V5 l) _- V! }; i) ]902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design8 V: E8 _6 A' C) d
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?4 Y" F+ d8 ~! Q7 t1 a2 N5 U
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
/ `1 b8 z, _! K5 V9 O [# U* y903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
! J1 c$ m% D: N$ Q904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable' n+ Y& y. ~# U
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
1 N" \$ v2 }# _2 P. o Y, a) i# d904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3( q/ T% r: y8 z# H
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
3 W( z1 j- b& B1 Y904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
1 f- u% Q, Y4 ?: o& X904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.32 Y. k7 t0 E1 H
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
7 q9 s. c$ n3 {, n- H905314 F2B PACKAGERXL Import physical causes csb corruption5 }- p2 o( a: u5 m% d" x- Y
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process. d0 Y& z/ i/ g+ [, J8 z0 Q
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible; k! A. w- t) _5 x( a
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues! Y R, G3 Y; n6 ]
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
! R7 l) @% v" ]4 W1 }" g0 b* F% _3 l906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.) ?& p8 ~& R' V
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
* g- g/ [+ D# Z3 @/ _% S9 p+ r906182 APD EXPORT_DATA Modify Board Level Component Output format- Q+ a5 a. t& O; x2 G( B9 V( M
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
1 H" V, _, E* z906517 PSPICE PROBE PSpice new cursor window shows incorrect result.+ o3 X$ S4 G4 I; W4 t# |; p: u
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
/ b& l" P8 l) X! }' W# L906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run$ C# u2 n4 f3 x' u
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging) q" J1 B G& B! ^8 \/ n4 N
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'% H; [' B% E+ C, {6 i6 M
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation, D& |" |8 I) E5 b! \
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin; i# H7 S$ w# o
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used. J/ t/ e2 o. {& I* L2 `
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
% d4 B, |' }' r7 ?# p K907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.3 q/ v; W8 _+ e9 D
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"5 k/ M- u- Y# Q5 C v
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31
9 b2 T8 Y# c& x" D1 q' }0 v2 [' Y907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
( v$ |7 V3 W; m1 g& G7 v$ M) [907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional, p0 a, a# v8 F( \/ W) t/ E
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
+ ~3 L4 y$ L5 a( b" i1 [3 {% r, j3 C908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.9 m' z( @( [. R! J2 r
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
( K$ |: {$ Y7 [: }: y! f908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3. c+ D+ K m0 V" v8 z S. }
908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
) X+ s0 k O! w: k/ ^908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
! L' ]! u( Z/ ~# J0 n0 W4 G908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place
* R0 z& ?: Z6 Z908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
0 M$ I# F; i& M0 G% w' _' E908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
5 c2 ]5 x" v5 q! Q- Q$ P, k908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
. v4 K- s5 j- z: p/ n: t908849 CAPTURE ANNOTATE Getting crash while annotating the attached design4 | s# n q( N
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
1 {* [. ^! r# j$ S; Q909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
' \3 l. ^" |8 M- K! j# m909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.8 S5 i4 ~: b1 e" I0 G
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
! ^( P+ G4 ~- F: U1 w909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
+ R* q( v" h2 L' e6 ?7 w% X909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning2 d8 J4 y. M6 y# p
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
3 f! \: h9 l \909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
# E3 v. \, X% r+ j2 Z. N0 v3 d910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.- @1 k& I& L* A/ j/ n% K7 z
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector) |4 @- ` a2 _+ [& T8 `4 s. r
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.' k( V% R. ~; E
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
) F8 j3 f% L& O1 D. ]7 |910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.# z0 U) I& I" a, ?! W
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
! s; r7 _$ ` c: ?) |, \6 m911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
L+ h0 F3 \2 ?! D* j; @$ z911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
4 k+ W. g! P8 Z- G912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
, f2 A2 G2 z. }$ ~9 c912459 F2B BOM BOMHDL crashes before getting to a menu H. L$ w; \& Y8 h. {; b! @
913359 APD MANUFACTURING Package Report shows incorrect data
7 ]% n" Q3 R( O" f3 X' B( m' Y j# r) a' N
DATE: 06-24-2011 HOTFIX VERSION: 001
/ u- \' N' f l7 ]===================================================================================================================================
0 @8 P* D# H V# ~ _; ?CCRID PRODUCT PRODUCTLEVEL2 TITLE1 x/ C3 y( [6 }* p6 L" W4 [
===================================================================================================================================- @% P0 f h9 }
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
) P& F. c ]9 g$ T298289 CIS EXPLORER CIS querry gives wrong results/ q% W( e8 H7 D0 D: s- W# l9 [
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
9 W5 C( ~2 p% @$ \432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
% n$ a) p7 |9 Z: r U+ r P; M% X443447 APD SHAPE Shapes not following the acute angle trim control setting.
1 R- j8 T( Q: n$ p. a473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam: [! _9 j6 C; l
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy, e( h0 A; p1 ]) y1 A( c. ?% o8 q
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.- V4 n3 K: \/ \$ Y0 q
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart: _" a/ c3 K3 d) Z4 W
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled4 N" t( Z# B; V6 n2 F3 ~6 s
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
& z$ }* n: o1 n0 V& ^% z644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
" n3 v g, U) V. U/ k645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board9 u" u' O I% c C" S
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.
; H a5 O. E" _# R+ z! a0 G( @, P763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
; ^9 T9 h m- U: c: b0 U770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers! P& F \ x& f4 o8 ?+ o& a. U
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets0 ~. [8 V- A! H/ G& R% e5 p
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
; ^9 }- y7 m' |& c' s3 H803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part* C# q: Y0 g. C" s' D% k# W. Z
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
" t4 Y K/ R; _( y$ r+ {" @809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
* ?# @; R, A, c" M2 F4 e+ C; l816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch2 s3 R- f" X* s3 p
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
4 p1 n- U- p3 ]8 E% I832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.6 D7 K4 l7 @$ m, G7 g
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL% ]+ {: z9 \0 u2 k% s/ ?$ N
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error# c4 \; G; c3 b8 a4 k/ U
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version# [9 ^: I# o! X# V, `
844074 APD SPECCTRA_IF Export Router fails with memory errors.: y' C+ X3 C7 Z Y+ d8 ?% s
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size- b V6 G& @7 ]( s, O2 Z
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
" J4 r: |( \5 x. {- [/ |9 M855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.) w) M+ L- @3 J
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs* [; u0 a; Y" @. j; n5 }
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
$ n, {& w% B# H1 I3 W, h866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line8 P( X6 G! w/ a5 H& U% w V
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF! Z5 ]. `3 R- d# r6 K( J
868618 SCM IMPORTS Block re-import does not update the docsch and sch view
( j) ^/ A6 j( H" }0 Q5 Y873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
( |) `8 v$ c6 `9 E! x6 U6 D) P874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
: U8 F' Y# c$ A" b8 ?874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command0 A c8 o x) X
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
' f" @, r. @% S& K2 ?) I875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l12 C8 J: f9 d' z; q
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net( ^5 c/ @7 I' i, _; T+ O5 P
879361 SCM UI SCM crashes when opening project1 P* Z7 \) z4 H
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
3 Z4 T. r2 V5 k1 l879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
7 u+ r$ m- w! a S0 b4 j5 v881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
4 _2 z$ l9 R6 e$ C9 C: F! G882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
" u& S4 _, q- l. [5 ^882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier5 w' R5 b% f8 Q5 R3 u
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
1 W" h% r+ A. _2 a# P882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement, Z, ]5 u) v$ ~" s, P6 ^( k
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component ]& V& G/ {$ t4 {4 O" ~% h
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
3 e/ L/ O/ I' Z/ H8 Q$ W7 o883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder: r( P2 ]2 y( y' }; s* [
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.! x0 b$ V- e: }6 O3 p& k% @
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
( _& f) d+ i$ `" c* J2 N' f' v% I885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations* n5 [- d) ?( }
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid* i* o* B& ?: R( F! g
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses5 u4 [/ H& m+ G( N
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
' O% U- t0 r8 H887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
0 @1 m4 }# F9 X4 z9 N' o887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
( [7 E3 L. P3 q2 v+ j( R888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
( z3 w* m0 [ e* c" K, n. O888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic# P$ \: Z6 N; b0 {. B; }5 {! }
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.: S$ ]; e7 r+ l
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board., t8 L6 L4 p& d4 |
888945 CONCEPT_HDL OTHER unplaced component after placing module- v3 x1 c0 y! }
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.$ `, V! M) x4 p( C$ A! q
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
7 V5 Y9 H7 P; X, X' @889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
& u4 q9 I9 e. Y$ I, C889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net3 X! S3 ^: O( v, ?) x7 F
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form$ J2 B2 A8 r; Z0 w& B8 _& u1 K
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file0 q. s2 T3 F, Q* J7 z. z. D8 }
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
9 Y& ?* U8 r! g! W0 Q1 E( O. A891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
9 w& q& h d9 e7 ]; _+ r( C892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
8 [, K+ [4 U) D V6 h892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?6 ^% U6 w2 ~; N$ o! e! F w( }4 _
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness5 _' q- _0 t/ q+ J' x, m
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
: S; h$ G+ X$ R1 g! q892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations' w B8 o; g2 Z' E& Q
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR- M+ D3 C; z( O6 X1 y& g( H- B' S7 x
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".7 y3 I: v2 J7 Z+ M0 R
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
3 p. D3 o$ G- _9 E" D. I893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board6 O: N$ Z0 U4 g6 \; T2 ^. H
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
# E8 S- Q; r3 H5 D2 x% x) z893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
, d5 S# T! y8 ~& M) ^- t0 \: w894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.* ]- j9 v, S8 ]! P
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
5 g3 Q* a2 P7 d" ]7 X+ p$ u, P1 a894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.. n/ H2 ?1 T; J L% ]) Q
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON7 {2 i, p4 }, |9 T) }
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
. h. W- L2 z8 [7 F4 ` l( i895757 APD ARTWORK Import Gerber command could not be imported Gerber data
$ R! ^3 S4 @" `& B3 d895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly8 |" W/ |- {% k5 s) j3 e J
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced! e- P2 e( j; T3 q
896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture0 f+ I$ F6 t3 a! o
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing p3 f7 v t/ l2 {6 o* s0 g
897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
0 E B$ _0 t0 f+ y, C897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.7 [+ O! K; ^: |
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
5 ]% p( E* r! \' ]8 t2 b899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof( N1 d$ T8 B/ [1 @+ q! ^
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.0 }* a* N# ^( ^$ T4 r. n: r
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
+ J0 f i) K# n" B3 f900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.8 z; k& W V/ M- v! o
900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
% ?: J C4 }3 U" N! c6 U901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
% U G1 j! D; n; k; ? e, `( y3 B901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong/ |8 ~! k1 n9 m% L3 H o6 N
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page) @# o9 g4 W* J) ]5 P! @( J8 Y" K
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
; ?; i' L* Z3 K. b8 [902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
2 X$ |, [% `* _) |* o902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
, j- p7 \! V. Z& E1 J+ L4 @902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization8 c6 s5 K$ N, y7 x, x7 `: z
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
9 L7 C, H9 m6 p) F; b902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes2 S# F3 _6 m3 ~+ |1 \
902909 APD WIREBOND die to die wirebond crash
$ c, E) d' Q y% v902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
; M& P/ K# {, o& Y! `, x903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline2 @6 X; p) @0 V1 ^
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement. e/ ~2 o! `5 N ~7 r0 i
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2012-2-21 14:58
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
发表于 2012-3-8 15:09
