Hotfix_SPB16.30.007_wint_1of1

T45524093

  z2 \$ c8 ^0 [6 |http://downloads.nordcad.dk/Hotfix_SPB16.30.007_wint_1of1.exe

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; \) {' q& U0 m2 _" h' y: }3 IDATE: 04-23-2010   HOTFIX VERSION: 007
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# ]/ b, D- e) W/ K3 I  p( Y; OCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
721859  ALLEGRO_EDITOR OTHER            update shape to smooth creates tmp file on remote file server working dir why?
740201  SPECCTRA_MENT_ IMPORT           Wrong stackup order after translating from mbs2sp
744797  SIP_LAYOUT     OTHER            Cannot Copy a connector (IO) symbol in APD and SiP tools
747831  CIS            CONFIGURATION    There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
747848  CIS            CONFIGURATION    Unable to configure CIS with Oracle database due to Capture crash.
% |, Z1 ?" x5 {, d' v' ], C/ v751372  CAPTURE        OTHER            Copy / Paste Issue in capture 16.3
, {2 r- u: \2 C* p757434  ALLEGRO_EDITOR MODULES          Allegro hangs the board file after creating Placement Replicate circuit.
( ^4 B3 @- G! P6 C& `0 x3 w759906  CIS            PART_MANAGER     Property copy from one to several parts doesn't work
760154  PSPICE         NETLISTER        Model parameter (Tj) is not affecting Smoke Analysis result
761177  CIS            OTHER            Error Message - Memory exhausted
( T) ]" R# U: Z1 x, {, c. S1 w/ W: N762602  CIS            EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
763677  APD            EDIT_ETCH        The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
763715  CAPTURE        NETLIST_OTHER    A long pin name gets truncated upto 31 characters when the wirelist is created.
: u3 {5 k0 M, m' Z/ X763878  CONSTRAINT_MGR DATABASE         Why Pinpairs disappear after closing Constraint Manager?
+ N, L( ]  ?4 M& n764020  CAPTURE        NETLISTS         Usernetl.dll has changed between 16.2 and 16.3
) U! t8 p0 T) F: |+ P2 B! y764101  APD            EDIT_ETCH        Perpendicular routing through a  Region does not work when the region segment is drawn at an angle.
; i! |! G5 Q4 k! |" f764200  ALLEGRO_EDITOR DRC_CONSTR       Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
764903  PSPICE         ENVIRONMENT      'Run in Resume Mode' does not work in SPB 16.3
, M# B) r8 ]+ z) Q' o) H$ E/ n8 b765206  F2B            PACKAGERXL       Unable to feedback subsequent pin swaps from Allegro
765319  APD            DRC_CONSTRAINTS  Identical Constraints in Performance Advisor question
765541  SIP_LAYOUT     SHAPE            Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
766147  APD            EDIT_ETCH        Resize/Respace Diff Pairs does not work on 45 and off angle
4 t  G4 ^1 ^6 n% l: w766337  SIG_INTEGRITY  GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
2 l/ f7 n6 s7 B3 u" A766443  ALLEGRO_EDITOR PADS_IN          unable to translate PADS ascii to brd in 16.3
* D7 s: U$ r! p2 ^4 ~& u: Q, n766581  CIS            CONFIGURATION    In 16.3 capture.exe remains memory-resident after exit
767161  ALLEGRO_EDITOR SHAPE            The behavior of Add Fillet command is different by Hotfix version.
; W* W4 r5 o( B/ A' O767217  SIP_LAYOUT     IMPORT_DATA      The Die-Text In wizard and it is crashing on the "Finish" step.
767598  SIP_LAYOUT     WIREBOND         Can't wirebond SIP designs as it just hangs.
; X# }7 e: x/ f767832  ALLEGRO_EDITOR DRC_CONSTR       Reducing Design Accuracy updates Physical Diffpair constraints wrongly
- d' `$ w6 Q6 k0 r3 S8 D7 a768822  ALLEGRO_EDITOR SKILL            axlSetParam return value is divided by 10 to the power of the design accuracy.
769150  CIS            PART_MANAGER     Update All part Status on a group changes 揇o Not Stuff? status to 揝tuffed? in V61.3_ISR_5.

huanxirj

楼主好强！！不过可不可以解释一下呢？我实在是不太懂~~~~~

llyygg

感谢提供连接

08181001

咋来得这么快呀,偶刚装好006,
( y- C5 O, ^* f谢谢楼主,先收下了~

mengshang

谢谢提供，只是win7 64位操作系统好用吗

tester1018

谢谢提供,
# u6 \9 s" I0 A# Z$ ~1 q出的還真快~

interrupt

真快，06下了都还没装

tzwhzf

我装了之后 启动异常，害的我指的重新卸载了再装。

hsypcb

我是WIN7 x64的，装上去PCB Editor 能用，Design用不了，只好又装回了005

hsypcb

谢谢楼主分享

weblibai

现行谢谢，以后下载

steven.ning

下了一个，谢谢！

zhouhua_8

安装了这个hotfix，之后capture cis不能使用
9 Q( n0 P9 X2 [. J% F具体可以参考
' U( }- c( Z& D" ~  |https://www.eda365.com/viewthread ... ghlight=spb16.30.00

zslic78

谢谢！安装完毕！

clk

谢谢！