PADS9.1即将催出

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9.02有很大BUG，所以MENTOR又匆匆修改了几个补丁，然后集合催出9.1，现在9.1已经进入最后测试：
PADS 9.1 Customer Beta 6 已经出来：
# a# W6 w1 g- T# yPADS 9.1 Customer Beta 6

0 x* \8 x) I) K- fDecember 2009, Install 12587
: H* _$ c$ ~( z6 |1 U

1 H# }- S2 N4 D* d, l, j# ~Please submit defects for products as instructed below.
2 g/ G3 Z8 z$ u' b-----------------------------------------------------------------------------------------
Defects for PADS Layout, Logic, Router and DxDesigner should be submitted to the Beta products on SupportNet,
$ o; {4 X3 B; Q; i( p$ ~
, c  q% Z* u4 Q2 v! U7 H4 W- U; Xwhich are BETA_PADS_Layout, BETA_PADS_Router, BETA_PADS_LOGIC and Beta_PADS_DxDesigner.
% u$ u' R6 Z  ?; q% A( a, v/ `' Q

***IMPORTANT*** - Known Issues and Future Changes
-------------------------------------------------
1. DxDesigner and related programs from EE2007.8 are now included in this release.
2. Archiver functionality is now available in the Tools menu of Layout, Logic and Router as well as DxDesigner.
3. During installation there is an error with the post install script "accuparts_dx_postinstall.bat".
' @4 Y$ t/ O! T( u0 r
2 v, B& H4 o! f; r" w! B4 ESee the reference notes below for a list of functional updates and current fixes.
6 z# L( h1 ]) ~  ?
Regards,

The PADS Beta Team
! H: O/ b! n; n4 f# ]# j4 C: h9 H


; m" R  \8 G4 K6 C0 g" t* B5 MSetup, Licensing, Installation, and Distribution
2 v$ z: V  ^; l3 ]6 p8 ^0 N* K------------------------------------------------
- Windows XP and Windows Vista Japanese are supported.
- Database formats for Layout, Logic and Router designs have changed.
- You are required to have a licenses file with an exact access date of November 1, 2009 or later to run this release.  To determine the Exact Access Date (EAD) of your license file go to mentor support net。
3 H$ s# m+ w" `1 R3 }PADS9.1 is a completely separate installation from previous PADS releases, The Installation
path for PADS9.1 is now C:\MentorGraphics\9.1PADS.  While PADS9.1 does not overwrite
previous PADS installations, you should back up your existing PADS installation, designs and
5 `, M  q  ^  r8 {) I; @5 Qlibraries prior to installing PADS9.1.


Fixes/enhancements for HyperLynx Thermal
+ u$ G: s# d" ^5 L----------------------------------------
9 i' V0 d, ~3 n" s' Znone

Fixes/enhancements for HyperLynx Analog
---------------------------------------
$ i! O3 y, D' m! v; bdts0100634577    Apex Engine doesn't complete simulation for Digital Models
' ~, c  O1 p& _( e4 D- c$ T- q" Xdts0100636111    Infohub Help & Manual Scope incorrectly says "Analysis - Simulation and Signal Integrity with HyperLynx Analog
  y7 z2 W% q- b5 ^+ A0 I9 B% Udts0100634078    Eldo MC78xx models are incorrect and do not simulate correctly
dts0100636035    The SPICE model libraries do not load when useing Eldo with PADS
dts0100608146    Exclude Component not shown in Japanese menu
dts0100608582    [Simulation Control dialog] :"DC Sweep Parameters" page --> "Add' doesn't behave correctly.
4 T* [6 t! d( S7 Y8 T* B# u1 ldts0100616119    .option tuning will override user value for eps
: n5 x( ?' N3 cdts0100631676    Incorrect netlist from distribution dialog
  \# {% A  I# Y8 Cdts0100608021    Exclusion should work hierarchically
  ~2 k- M( u; Odts0100614981    Eldo behaves different than the other netlist formats
6 N) A1 ~: ~5 c  C4 d) Ydts0100615983    The VHDL Netlister should handle the (Read-in output) by creating an intermediate signal
9 Z! f4 _' E0 H: [' Z5 kdts0100615994    Wrong netlist when symbol pin number is greater than model port number
dts0100618238    VHDL netlister does not handle ports properly
dts0100620878    Wrong VHDL code with component array
6 U5 q0 e* d$ u& Q: U3 n0 kdts0100622857    [Netlister] Netlist error in ports connection with buses
dts0100630659    [Netlister] VHDL netlist generated for the attached project is incorrect
dts0100632875    [Netlister] Output port is not mapped correctly to the bus connected to it
dts0100632876    [Netlister] When Port name is same as bus name, the buffer name will be incorrect
dts0100633267    When switching simulator between ELDO and HLA, dxnetlister.ini lost [SpiceHeader] information
) P7 G. Q' v' @; q& L

Fixes/enhancements for HyperLynx
--------------------------------
% J1 ]! q% x1 kdts0100629862    HyperLynx BoardSIM export from PADS Layout places plane areas within signal net definition
, `4 t3 B& I! g4 F; v7 D+ `0 ?4 r
   
/ e9 V% r9 ]7 n: l% X7 K- WFixes/Enhancements for PADS 3D Viewing (Note: 3D Viewer 2.0 is included in PADS 9.1)
6 \0 m6 P4 h" [- C1 v; x4 O------------------------------------------------------------------------------------
  E6 e1 |- m, M$ i7 Q5 i' u7 }dts0100605690    Layer 20 (footprint courtyard) is used when generating the 3D view.  This causes problems with the new 3D viewer
dts0100635846    Component heights are incorrect


Fixes/enhancements for PADS Layout
4 ?+ w7 x/ e% H! y- G9 g----------------------------------
dts0100592339    Netlist from DxD is wrongly loaded into Layout if Unit attribute in DxD is set to Metric.
dts0100621636    PADSLayout hangs when you want to substitutes part with Decal that has 'increaded Layer mode'
dts0100601402    Time stamp for Part Type on pcb design is not updated when you modify attributes.
dts0100631451    Change label in HYP Export dialog box
5 b1 |6 \% [% m4 ^/ K9 gdts0100544158    Poor outline information sent to 3D Viewer - Beta 3
dts0100547218    Gerber preview shows short in the design. But there is no errors if we run clearance check.
4 d- |  n6 d3 [dts0100593049    PADSPCB_Decal Wizard -   RMB opens main window popup if cursor is over a data line or title line (Defect for 9.1)
dts0100593100    PADSPCB_Decal Wizard - Default layers for outlines in the decal wizard options should be Silkscreen Top, Assembly Top and Layer_20
dts0100593106    PADSPCB_Decal Wizard - Selection pop-up on cells is appearing in the grid controls of decal wizard and decal wizard options dialogs.
( p7 @* V: ^+ \* `5 _9 S5 m0 edts0100593107    PADSPCB_Decal Wizard - Decal Wizard: Create crosshair as two "L"'s (instead of two crossing segments).
dts0100593110    PADSPCB_Decal Wizard - Decal Wizard dialog: Default button should put some values for component dimensions in the "Land Pattern Calculator" group.
dts0100622131    Pads definition on solder mask is incorect for through hole device type generated by IPC decal wizard
8 Y& u! o: p& i8 v, z% a4 Pdts0100622230    Incorect dimention name in the grid
# q3 v6 D+ `: F1 w& K7 hdts0100622475    Placement outline is shifted for generated decal
dts0100622697    Preview window displays colors incorectly
8 I: G. h3 @8 s, f0 [  h( t0 Sdts0100623701    Notch for assembly outline should have separate control checkbox
dts0100623736    Rounded corner radius is incorect for pads on solder and paste layers if mask expansion is used
dts0100623783    Generated decal is collapsed for those specific parameters
dts0100623797    Tab order works incorectly for wizard dialog
* C$ M' T# E% w" S2 z( T8 ^& L- Xdts0100624535    False pad to pad clearance error is indicated
9 ?0 ?7 L7 i" ~- C2 ~5 H4 _/ rdts0100628883    Distance between pads and silkscreen is incorrect for quad decal
dts0100629011    Some pads are not rotated for Polar decal
dts0100629304    Preview window blinks after pressing default button in BGA tab
/ ^, w# H# f9 d4 k+ sdts0100632350    Units groups in the decal wizard and wizard options dialogs are NOT in synch with unit setting in the Tools->Options dialog
dts0100633384    When a configuration file is missing used gets a misinforming message
  q; l+ g9 B: {  t9 C. G- F, fdts0100629345    Polar tab does not respect the silkscreen line width parameter
dts0100582679    When the "Remove unused pads" feature is used, pads within "copper pour and plane area" keepouts are not removed.
! _1 q" K8 ~- \& K  W5 S' h2 Udts0100620173    Runtime error while doing Forward to PCB.
dts0100634090    Runtime error viewdrawlink on update PCB
: R$ N  Y+ n7 N8 Hdts0100472613    Not possible to change parttype with PCB-Decals with different number of terminals
: a/ x" g9 f4 f1 ?dts0100480393    Pour Manager does not consider board - Copper Clearance Rules
7 m+ W: `- @: f% U- z( E4 C* M* j: Ldts0100570786    Bad flood data creates short across 4 nets which Verify Design did not catch
dts0100605615    Boldface not used correctly on "PADS Layout GUI Reference  > Options Dialog Box, Grids Tab" help page
dts0100633511    Change the help menu item to point to a different book
+ n, ?) S. ?  \' udts0100632059    Altium Designer 2006 file will translate in V2005 translator but crashes at 75% in V9.0.2 translator
dts0100593860    DXF and IPC export generate Fatal error occurred while exporting design - operation aborted
dts0100473144    Length minimize during move will not work when connection is established to partial route or via.
, i- R* h+ Q0 ]6 F- E  U& Cdts0100629626    MACRO - When I run the attached macros, the result dialog box doesn't appear. In previous versions a window would popup listing the number of errors found.
dts0100627987    When modeless commond "zc" is used, PADSLayout is freezing.
8 l; m1 k* b5 l0 |0 gdts0100633930    Too crashes when we export ODB++ for preview.pcb
dts0100636557    ODB++ Output error (Fatal error: layer -1 not exported!)
  u% x8 Z5 D' \3 |# edts0100527420    Tool allows to create 'Thermals' for SMD Test Points, which leads to series of issues.
, y+ w! ?2 \9 fdts0100630528    Create PDF - Graphical error in copper (Beta 3)
dts0100631593    Create PDF - Some Ref Des are rotated (Beta 3)
( W  y3 E0 x: O+ a# Odts0100631669    In PDF User defined Untipads are not added on CAM Plane layer
dts0100631920    Create PDF - Remove Bookmarks for components not included in PDF file  (Beta 3)
dts0100635884    Creat PDF process request hundred times for component that does not exist in library
dts0100496801    Reuse Copy loses Flood Priority, resets all to 0
" K* [( Y- }' @" mdts0100419975    Remove unused pad does not work for nested planes where the outer plane net was used in the inner planes
1 Y! b5 G+ ?' ~9 Q2 K. t7 t9 p: v  w9 cdts0100636198    Crash when removing via from routing via list
2 H* w& Y# R8 {) y. c  V6 mdts0100637331    Pads disappear when zooming in/out
, p. g; @2 X7 d0 u: hdts0100635066    "Fatal Data Base Error Number 2012" and crash during opening a design in non licensed mode
dts0100600676    Picture and information about UFL dialog window should be updated in FSP (or implementation should be changed)
dts0100621629    Strange message appears when you perform UFL in Layout.
dts0100634588    Update From Library creates Undo Checkpoint even if no changes are made in the PCB Database
dts0100634589    UFL dialog: Remove Selected Items button should be ghosted when no design items are selected.
dts0100634608    When you import an ASCII file netlist into a new pcb database the decal and part timestamps are not included.
dts0100634609    "B.    The part type section contains 6 parts that show ?Different? in the? Content column ?but only one of the six has a value in column ?see line?. Should have a line number on all 6of the items that sh..."
dts0100634613    The "see line" of Part LITTLEFUSE-V18AUML2220(located at line 89) shows 195 in the "see line" column but it actually starts on line 193.
4 o# N7 T2 O0 L% K; Udts0100634615    Timestamp values are not shown in the Part Type Summary.
dts0100634616    Line 136 should not truncate names. Wrap the text to the next line or show the entire value.
dts0100634620    "C.    Line 644 states the Attributes in the library are 16 and the attributes in the pcb are 18. The actual decal has 18 attributes looking at the actual decal in the library file lenny.d"
dts0100634622    "F.    Looking at line 682 685 686 the counts are equal yet the comparison field shows not equal. Each of these should have additional lines underneath them showing the actual item that does not compare. ..."
( Q3 U& K' P- `7 {7 Hdts0100634637    "Looking at REPORT-LIB-UPD-ALL.TXT contains the following errors. (Generated from PCB File LIB-UPD.PCB). e.    Line 11221, 11336 states they are not equal yet the 4 lines below that are equal."
; V, K4 P( y6 \7 jdts0100634646    Even if you update all the parts using the library update to update them there are still errors when comparing the library to the pcb. Please see REPORT-PARTS-UPD.TXT
: ^3 z/ }- b' k% p+ V$ Z" udts0100637697    Parttype timestamp in PADS Layout is not correct if "Send Netlist" is used - (Beta 5) Could be related to dts0100634641.


Fixes/Enhancements for Logic
8 l" \& w* B* O; d# O5 ]" b----------------------------
dts0100623556    Component attributes with a value can not be emptied in Edit Part.
4 P4 M- m' q8 q- ?8 Adts0100629839    Global switch in options to turn on/off place holder attributes in Logic.
; a2 l1 l( x& Wdts0100591808    Update Logic Sample Files
dts0100428973    ECO/Compare reports No Differences Found when one of the files is read only-should indicate it needs write permission
dts0100592901    0906021756_PADS_LogicCrashReport
( }8 m" R' X7 xdts0100533663    Deleting vias in Via Definition > Via Setup does not work
dts0100630556    Autotest detected: "PIN Decals" instead of "Pin Decals" in Update from Library dialog box
dts0100623987    Fatal run-time error
! `7 D1 v) ^7 R  e- m- Xdts0100579379    Automation method ExportNetList wasn't modified when the number of items to select had increased
dts0100619394    Regression: If you edit a part from the schematic and add an attribute the attribute is not included after returning to the schematic
# W( L) i) P* B* s  n, b3 e% e" sdts0100614860    Getting error message 'Fatal Runtime Error' when I try to generate File > Report > Unused
dts0100349358    Adding Classes with spaces crashes Logic
dts0100574637    More than one net is unknowingly selected in the rules after performing a specific set of steps.
$ `/ ~/ [/ |# q& r3 I; Q/ xdts0100537702    There should be a Select list for each Item. Right now, only the Pin Decal has an individually selectable list.
dts0100537705    "Update from Library" should be on context menu when selecting a part or parts.
0 \5 J( S: d' a6 Y- [9 rdts0100552427    UpdateFromLibrary cannot handle same part types with different attribute values (in report)
dts0100571175    UpdateReport detects hierarchical sheets as CAE-Decals - Beta 9
, t6 Y& d- u3 W" [# @dts0100579630    Alternate PCB-Decals still produces false differences in UpdateReport - Beta 11
dts0100593092    PADSLogic_Update from Library - ENH:  indicate library name in the report (for library decals, parts)
dts0100618873    Header in PADSLogic UFL report should be updated.
* y+ `! ~; O  [8 t

Fixes/Enhancements for Router
-----------------------------
# `% v+ C3 q+ t4 n; ldts0100628438    Saving file in pads router causes fatal error.
+ J& C: L# M6 k7 Xdts0100450331    Why can't Blazeroute.ini be populated with the new options in their default conditions, so users don't need to type everything in?
" M8 h. ^# P: p% F0 Bdts0100531461    Incorrect parameters in Router
dts0100583129    Crash dump
9 x: e7 T8 y  y% i( k5 wdts0100635895    Design verification scheme list not work correctly.
dts0100493262    Default Windows dialog is displayed for some controls
9 y3 D( w- T0 T( Ldts0100634385    Library Not Registered errors when PADS is installed to a directory with spaces
8 O, G. r" z8 S7 F( m5 c0 A

Fixes/Enhancements for Install
------------------------------
dts0100498605    Need improved handling of the "lost license" scenario in PADS
5 Y  s5 b# ]% }/ k9 \; Ydts0100569313    PADS "Hardware Key Utility" program to make testing keys and installing/removing drivers much easier for customers
dts0100621527    While installing the program got error message "C:\MentorGraphics\9.1PADS\SDD_HOME\common\win32\lib\MGCLibDataGrid.ocx" failed to load for Registration.
$ h, y, C- F) L2 y  F" }( N1 `
: F2 p: V" q( O4 q- ~; R' ^  r
Fixes/Enhancements for IO Designer
4 y' e2 b7 W7 S, w& C. E* O' S----------------------------------
dts0100635950    Layout form Allegor is display incorectly.
. a: R- R* C8 e. d2 P# mdts0100635963    Missing brd and hyp filter of types in select path to layout.
$ y3 `# F* C8 j5 n5 F$ ydts0100637587    IOD display only current fpga on device view (Layout import form Allegro).
dts0100638335    Cadence IOD8.2: Got 'Unknown flow!' error message when trying to import schematic design.
dts0100602206    IOD not outputting good Actel PDC file
dts0100633957    Wrong recognize diff signal form QSF file
) n$ B  `& Z/ T' f$ v0 D2 M; odts0100625917    After import QSF some differential signal are doubled
dts0100625992    It's impossible to import properly diff signals from pin file if it's use '(n)' convenction of naming diff pairs.
dts0100616628    'configurator -uninstall' didn't remove IOD entry from menu start
dts0100621897    Poor support for IOD installed as single product.
dts0100630357    EE 8.2: Installting IOD 8.2 alone would not register the product on Windows.
- ~) ]) l7 k9 B" Idts0100616905    IOD does not dump tcl command while import signals from spreadsheet is performed.
dts0100636590    Iod deleted all project files.
1 ~; t* c/ G' G; w/ X) q2 m# wdts0100629434    IOD is not responding for over 13 minutes after selecting GND signal.
dts0100633035    Cross probing :  highlighted wrong signal in IOD while selecting  net in DxD
5 m2 L% F: o. Ldts0100625292    Pin swaps are not imported
dts0100616652    IOD hangs after minimize die size is run in specific case.
/ v7 r$ `* F6 S' s6 \* Y2 Tdts0100615802    Documentation for IOD8.1 should be improve.
dts0100632600    Documentation incorrect in regard to Symbol Wizard.
dts0100614543    Write to Local PDB file is not remembered
dts0100617368    PADS9.0.2 The builtin 'sym\bi.1' cannot be exported. The path doesnot exist.
dts0100619265    PKG_TYPE and SIGNAL attributes are not exported to ICE in pads flow
' E  O0 l* R$ Y  }5 Adts0100619614    Differential buses are not connected on the IOD generated schematic.
dts0100630977    Remove design doesn't work.
dts0100632139    EE IOD8.2: IOD showed a fatal error when running run.tcl.
dts0100636406    EE IOD8.2: IOD crashed after export_all_schematics command was issued.
9 Q. Z' f  D. R7 h2 Qdts0100625329    Importing assignment for diff signals from dxd project does not work
dts0100632195    Schematic Update is removing and not adding any power, ground and/or config pins defined as signals and/or added to the PCB symbols in the DxD schematic.
dts0100615847    NSE seemed to crash on the 'exit' TCL command on Linux only.
7 M1 j/ Y/ M$ t* @2 J# vdts0100617458    De-scoped I/O Designer for PADS Suite
dts0100620002    ANALOGVCC is migrated incorrectly
' p- \' T, w. A' E, n- n4 a! bdts0100620440    Inconsistent behaviour in creating differential signal name
dts0100624825    Spread functionality of Types Compatibility options for HDL signals
dts0100624857    "Project could not be saved" because design name has space character.
' j" h- U  W! V* C2 Y: Mdts0100626736    Environment variable in .prj file not supported
dts0100632352    Llicense dialog - empty license options in 'PADS I/O Designer'
5 j& |/ r- w) P+ ^dts0100633373    SSO value is calculated wrong for differential signals.
3 I6 P! I8 \) @" ]# l  cdts0100635946    Migration of old database should be improved.
. u/ I) }- ~/ e. Z- hdts0100620449    Duplicated signals after importing from HDL and QSF
: ~" ~1 K9 c9 W: O) N0 K4 jdts0100636022    Crash of IOD while importing vhdl entity.
8 e$ T- j- \( {: i" Ddts0100616013    Wrong HDL created/exported
dts0100617953    Space character in design name makes problem for IOD.  Error: Top level must be set.
- p; G! g- G- I2 J; fdts0100633055    Import PCB Design Wizard: Whole signal is unassigned when one pin type is not compatible with signal type
dts0100597469    [BSXE] Importing swap in lpc database results in broken connectivity if component database is not synchronized before
6 }5 h+ f  o# O$ R' ]6 S8 Adts0100616740    Background on Layout view is always black on Vista 64
dts0100621328    Unravel on my design with diff signals causes error messages during applying scenario
dts0100630751    Library parser failure while importing schematic into layout database.
dts0100633294    Partition name is not displayed on Layout Setup window
dts0100633924    Signal names disappear on connectivity window after importing pcb layout
* ^3 A1 S. M" F! _! ^0 Adts0100615858    IOD8.1: IOD crashed on the TCL file.
dts0100616812    IOD8.1: TCL command, exportsymbol, resulted in an error.
7 Q9 c' _& s: J5 b0 Sdts0100618901    Improving TCL script recorder
dts0100623194    IOD8.1: TCL command selectsignals A<15:9> caused IOD to crash.
dts0100631902    License dialog is empty on linux after running IOD (refresh problem)
+ q0 C, z; Z. Mdts0100632077    EE IOD8.2: Available license options were not shown for the full version IOD.
dts0100632627    Some option related to die database are redundantly displayed in Tools menu for other databases.
3 p0 Y- w9 P8 d6 p5 h5 ldts0100633752    EE IOD8.2: IOD crashed on running the TCL file on Linux
* ]4 J5 P9 S( Z$ L% xdts0100634470    EE IOD8.2: IOD crashed when I tried to use TCL commands to select signals after running a Dx VBS script.
dts0100635370    EE IOD8.2: IOD crashed with C++ Runtime Library error when adding a new FPGA design.
dts0100638815    IOD crashes while openning customer's database on Linux.
1 y$ ~5 R, r: O; B  odts0100597062    Export to AIF from package db  is not required after applying swap on layout db
8 z2 o7 ?5 M2 ]0 F. x3 Ddts0100607448    Import package cell preserving assignments where possible
& N' `6 K: v3 k3 J" B, y  z% hdts0100628060    Error message after reimporting cell into package database with diff signals
dts0100629676    Unassign all => cannot unassign signal 'diff_test' - signal diff_test doesn't exist
& a& D( ?2 P5 g/ Y) ndts0100605036    Types Compatybility does not support an assignment exception
( r+ N2 b  U; J, \" xdts0100619916    There is no possibility to assign differential signal to pins 8 and 9 in Altera's device.
dts0100624059    IOD is not responding while assigning pcb signal with Shift pressed.
1 z6 A/ H! Q9 odts0100632373    Error while import  Netlist file (Spreadsheet): .csv, when signal type charakter are small
! D+ c. X  `, B% m, ~4 ndts0100632383    No assing differential signal (but no DIFF type) after  Import Netlist Spreadsheet file: .csv
+ v- ^) I) L( ?! |) u" k. hdts0100632619    Cannot assign output IO signal
4 m1 ^& e7 p9 s; K# O" \dts0100623389    'View pins from other devices' doesn't show common pins. Pins list is empty.
dts0100635506    IOD is repositioning windows constantly depending on cursor position what looks like IOD is blinking.
dts0100621902    Database Settings not prompted when loading FPC.
: j" |. a$ A1 ?' W% j2 q) vdts0100631933    Creating net-list project ends with error
/ i; W3 ]' H% R( s9 K6 s5 rdts0100633129    EE IOD8.2: Got an error on Linux: vmwlm: [11:14:40] error VMWLM0301: License server not found.
: t5 M1 [8 R  Sdts0100633480    EE IOD8.2: IOD failed to create a new project on Solaris.
dts0100626020    Rule engine operators have incorrect English
1 J+ o; |& f! J4 S$ w4 g: udts0100635228    Input pad with INPUT TERMINATION has to be at least 1 LAB away from differential pad.
: s- G& ?- c3 P/ }& z4 @9 N* _dts0100635867    Rule: Single-ended output and differential signals assignment" work unproperly.
dts0100619597    Unplaced tab improperly shows connectivity problems in some case.
/ Q1 R8 p; D+ z7 R$ b6 D% N* edts0100619601    Symbol Wizard does not place all signals on PCB symbols in specific case.
7 p% v. n! D! W% pdts0100619941    Wrong information of selected differential signals.
dts0100620427    Corrupted database structure
$ K% Q  u, p, X+ U, kdts0100619606    After splitting bus signals symbols become broken.
3 W) Q4 W8 `( I2 bdts0100619852    It is not possible to exit from mode of adding items (like arc, circle) with ESC key.
; X4 q; z7 R$ |7 M& G+ X0 B6 wdts0100632577    IOD writes to transcript some redundant information while symbol edition.
; s+ E( |" I9 H3 o: W3 qdts0100618530    IOD crashes after manipulating signals in the last step of symbol wizard.
dts0100619946    Symbol wizard doen't generate symbols with differential signals in specific case. Refresh problem.
( C1 @; f: J) k0 h& s2 }dts0100619965    'create bank power symbols' is not set up after rerunning symbol wizard.
1 t: p7 s0 T! H' }% ^dts0100626048    Sym Wizard assigning incorrect power signals to pins.
dts0100628170    Broken PCB symbols after updating.
dts0100629352    Symbol Wizard settings 'split only pcb symbols' were not stored in fpc.
dts0100632906    Design tool selection dialog is redundant because it is determined before project creation.
dts0100635477    IOD crashes while Symbol Wizard performs symbol update
$ R' f2 y, O$ c7 G% m9 Gdts0100548702    Synchronization wizard in relation to Export cell from die should be corrected.
) d% c+ ^1 V6 m& P0 }dts0100596151    Synchronization needs to be less sensible. Moving non-IOD symbol shouldn't request import necessity etc.
dts0100599155    [Synch. wizard]Export Connectivity table is not available on Synch. Wizard
dts0100606842    Everything is matched, however SW indicates, that synchronization is needed.
dts0100614895    Gray synchronization indicator sometimes blinks
: b4 q3 c3 X! y- d) B3 W5 Mdts0100617886    IOD does not request updating symbols after unraveling (some assigned pins are not placed on PCB symbols)
; [8 h, M' [, \- m2 N' T9 v+ {dts0100617937    Synchronization bubbles are yellow while no tracked file export/import is needed.
) H. d# N! x/ E/ ?. @* Udts0100619881    "Document needs import " during exporting schematic for all components
! w- _8 Q" ^1 @7 [) t2 o: xdts0100624493    [Synch. Wizard] Tracking check box does not work properly on Files View for DCDV files
1 h: s9 I, k; t) M: Adts0100628627    Incorrect export sequence: CES and schematic, but should be opposite. Lost constraints.
0 ^) \0 K" K9 \+ [9 y9 H" A* H# s4 Mdts0100628925    [Synch. Wizard] Connectivity Table checkbox is sorted and causes CES disappears
dts0100631718    [Synch. Wizard]Import schematic is not required on new layout database
dts0100632062    Synchronization wizard contains not added files just after creation fpga database
  e) v3 U& O  ]( n+ B+ l- {  tdts0100633995    Lack of 'update graphics' in Synch. Wizard for Schematic Design import.
dts0100635491    Import schematic is not requested in synchronization wizard after it is packaged (refdes changed)
dts0100620177    Poor results of unraveling for attached testcase.
' R" ^0 P* I; r0 J% Q% [dts0100629113    Unravel of crossover nets is broken.  Immediate fix needed.
dts0100631688    Unravel on layout database does not work
0 {  a0 E& [6 N) j8 a* X5 kdts0100491672    IOD crashes with PROLOG SYSTEM ERROR when unraveling nets in device view
. ^: o/ ], \2 }; B+ ddts0100636192    Broken connectivity in Device View - Synchronization Wizard suggest no action. Database corrupted.
0 k- X  {9 }* {$ q; L, c  Qdts0100632012    Incorrect warning message during export to UCF file.
/ T/ Y: d3 f8 f. f" I0 Gdts0100633340    Change default bus brackets for Xilinx UCF.
dts0100614926    Please add support for ISE 11.2 library.
dts0100616172    IOD needs to support the Spartan 6 devices.
dts0100368440    IO standard has not been removed from ucf.
dts0100622444    Redundant signal is imported from ucf: mcb3_dram_dq.
dts0100622447    IOD should not remove from ucf: TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  2.5  ns HIGH 50 %;
# `4 I) |( Q% P3 A- P  j6 `' y
, i' q. c$ m& S" `# y  v9 f" U
. w! T( X" u9 A+ B3 z) L6 ^
# V5 J' J, h( u+ n; Y' MFixes/Enhancements for DxDesigner from EE2007.8
" C9 i( e% p" U" v-----------------------------------------------
) t0 c+ |- H% {) W+ {dts0100586982    ict viewer has a menu pick for slice and dice, but no documentation for this function.
% ~  z+ r4 A5 A2 g0 j# r, Adts0100566586    Icon for deisgn path for additional symbol translation in Translation result dialog  is wrong
dts0100567745    Cadstar pin types are translated incorectly
dts0100592920    CCZ output: Text has wrong orientation in CCZ file for symbols that have been rotated 180 degs or flipped
8 z' I) o, o& c" H% Ddts0100633799    Verify: drc-201 reports an error when there is none.
3 @% D6 X/ B* Ydts0100595040    Diffpair Restrict Layer Changes does not BA by existing ECO file
8 B/ p! f, T0 e: gdts0100619515    It is impossible perform BA using DxDesignerLink
" }, ~' o9 b/ D8 @  odts0100633269    DxArchiver is completely not usable for big designs
6 m7 Z4 r1 t1 _3 x% kdts0100627152    The selected component pin object can't be got.
dts0100636979    DxDesigner crashes when quit command is invoked and DxDiagnostics is running
0 H9 J* N# }' r8 [4 y. K% u* v& Mdts0100637220    DxDesigner crushed when attribute is added by Automation Comp.AddOats / Comp.AddAttribute.
+ ?1 d* X+ a/ D* t; V5 ]dts0100631832    Launching Dx resulted in an error of missing prop_reuse_gui.vbs.
dts0100626155    While crossprobing pins in Expedition, DxD crash. Scott was in DxD as well in the page that was being crossprobed to at the time.
5 G. @# D, G9 r& Wdts0100631134    Documentation incorrectly refers users to circle object if they want to create an ellipse
7 p& K8 |- G9 l1 e# C5 idts0100614450    Live Verify fails when using the option "Use symbol data from Central Library".  This appears to be a regression from EE2007.6.
! M; o" X( @' P* |dts0100614912    ListBoxes to create query on dxdb grid display always all values from specific column during query creation.
% b. [; |; y5 d% ?3 d2 f8 |3 Adts0100615165    Japanese menu problem: In the pull-down which selects the slot of DxDB, displays of "Slot" translated into Japanese are not all displayed.
; P5 p& Y0 B7 Vdts0100616337    "Part Number: invalid identifier" error during verification with oracle database when "Use symbol data from Central Library" option is set.
dts0100616340    "Query is too complex" error during verification with some central libraries and "Use symbol data from Central Library" option set.
dts0100616953    Closing and opening DxDataBook may cause disappearing icons on CL view tab.
# K' U' a( L3 ?' v3 R5 j- G" odts0100616993    "Query", "Criteria" and "!" buttons are disabled after loading component.
4 L- T( d3 k: U" b6 Sdts0100617241    Export symbol(s) works differently if run from DxDataBook pop-up menu and NSE File menu option
, t2 m& \8 D& \) z% Gdts0100617992    There is a error after selecting tables joined horizontally.
dts0100618179    When placing components from DxDatabook it don not change "," comma to a "." dot as it do in 9.0PADS, this result in error when doing netlist.
dts0100629771    The query can not be created on the grid after selecting <ALL> library.
6 E  }9 N* D/ x3 Q* kdts0100629777    The verification buttons in databook can be enabled with Interconnectivity Table in one case and it can cause errors.
dts0100632306    In a Netlist Flow Project we cannot Select multiple Symbols in Symbol Tab of CL view of DxDataBook
dts0100632348    A message error is displayed during query creation on the grid for ALL library in some conditions.
! q( q' C0 U! L. M0 `/ rdts0100632402    "Clear the Current Search" option does not clear a grid displayed for <ALL> library.
# P$ x3 q1 H+ w/ w' m" C$ ndts0100632407    Button 'Enter user / password' is truncated on Japanese WinXP
) s- ]% W" J0 \( b% d5 y* Y8 h* gdts0100632412    "Remove Condition" does not work in <ALL> library.
dts0100632708    Verification in DxDatabook crashes viewdraw(regression to 2007.7)
. f/ v- A$ u# Y6 W1 F; t2 S4 C: ydts0100634366    Crash library wizard during creating horizontal table for expedition flow.
3 a7 y& Z9 d  h6 W* A, \) h8 x2 Y3 zdts0100637275    Crash during hierarchical verification on specific project.
dts0100372438    DxPDF EXP2005.1 generates smal dots instaed of text on Solaris 8 and 9
dts0100541964    DxPDF pager order does not work based on the scout SHEET order property.  Please reference DR 541962.
+ v' ?4 k& {4 t% qdts0100631034    DxPDF crashes if "Schematic Sheet Order Property" is used
  f8 J; S5 E, C* Bdts0100633031    Please correct the message  'Genration ICTs to PDF document (with conversion ICTs to schematics).'
dts0100602277    Pin number will not be displayed if Pin Label are either lower or mix case.
) b) A  C0 E4 w2 q$ s4 b) n9 ddts0100603902    "Add Missing ports" on an IO Designer generated schematic for DxDesigner the ports are placed outside the schematics.
1 p& @. |$ A  J7 S9 odts0100608356    Cannot read correct coordinates of scaled symbols in DxDesigner
dts0100611157    Part View place with slot fails with lowercase pin names
3 B$ i& \9 y8 c7 Z' R: u" s) i# cdts0100615128    In the "Find and Replace Text"dialog, the "Select properties only" option is not translated into Japanese.
dts0100615499    Japanese menu problem: "Select object > RMB > Pop-up menu" dialog has some issues of a Japanese translation.
dts0100616656    Problem with move schematic
. A% W# n! r& a! j6 X& B0 Ddts0100616682    Multiple Signal properties are lost when importing ExpeditionPCB netlist design to ExpeditionPCB iCDB integrated flow
dts0100616955    Symbol is not updated on schematic when editing it in NSE
3 Y8 {) p5 x: P3 @+ J% s- fdts0100617637    DxDesigner must support metric symbol format
5 D$ \/ o4 z, ]3 m, \+ s' g* ndts0100618285    Properties addin does not show a name of a net ripped from a bus.
dts0100619905    Clear Backups should be inactive for a read only schematic.
. C# f/ @7 ~3 z! b4 T' adts0100619942    iCDB error when placing an updated symbol
dts0100620246    Escape does not apply to Rip Net command
9 M  R- U1 X& \  y' A' Fdts0100621606    Update bus signals removes one of the bus names
' w9 [3 g  I: b# idts0100621892    unnamed bus segment created after renaming a bus
! j2 p+ A( H( U/ n8 T, j3 gdts0100622476    Push Schematic does not reflect sheet order
' n0 d" \' u6 z- C/ ~dts0100622848    DxD Diagnostics reports invalid net errors after moving a component
dts0100623038    It si not possible to add ICE Reuse Block to schematic
dts0100623061    Enhance Add Properties Dialog
dts0100623427    [Linux, Solaris]  Show Strokes option doesn't work properly
5 l6 N, ]2 F$ [dts0100624036    'DxDesigner application has encountered a problem and needs to close' is not closed when restart is chosen.
5 S! F6 r! t7 J1 J2 N% I" Mdts0100624188    add special component; [esc] does not work
! T& X, \  s9 v9 c& fdts0100624193    Change the message issued when a user types an illegal regular expression
# X; `# _: _; M7 Wdts0100624578    Endless bus created when connecting to an off grid component
dts0100624782    Symbol of the array component contains block name.
dts0100624866    Invalid global net created
dts0100624886    DxDesigner diagnostics fails to correct errors in an imported design.
8 ~: K" }+ ]1 r4 ^; _( @dts0100626698    While crossprobing in CES, DxD crash.
dts0100628557    viewdraw crashes when there is no write access to WDIR
dts0100628735    Error 1287 when trying to delete bus segment. Diagnostics results in schematic that cannot be opened in schematic or block view.
+ g# A2 t' S+ ldts0100628911    Modify delete sheet message when this option is chosen from the Navigator
6 x8 W" }& `( f  edts0100629037    'Error 1287: iCDB database update error: Invalid parameter' when updating bus signals
dts0100629072    Select all symbols on a sheet and deleting the Ref Designator property values, wrongly adds Ref Designator property to symbols that didn't have it previously.
. `& S6 ~  g) ^9 ]6 A- Hdts0100629389    DX2PADS changed interface - update in DxDesigner is needed.
dts0100629746    DxDesigner Diagnostics large memory allocation on this testcase
dts0100629772    Buses and bus rippers disassociation when moving a circuitry around
2 _  o" ^$ T5 ~6 p' m$ @( ~dts0100629789    Connectivity errors in a design created from the scratch.
dts0100630095    Shorted nets after renaming a bus
# o  W: V3 M  p9 Pdts0100630174    [Linux] DxDesigner crash when I press Undo
' q( ^3 t3 m3 N* qdts0100630197    Diagnostics error after changing bus ripper connection using 'Net is being connected to bus' dialog.
9 Y' b8 f# U- T( I( Udts0100630199    I get Commit iCDB database transaction rejected. Reloading project when I choose rollback
( u# M+ `- Z9 zdts0100630678    Wrong connection with GND and diagnostic errors after schematic modification
dts0100630683    I get GPF when I press Undo
dts0100630691    Incorrect global net name after merging two nets
dts0100630706    Wrong connection has been created after updating bus signals in the project
dts0100630958    "Push to schematic" does not work after using "extract schematic" during placing new block (regression to 2007.8.12157)
: ^( N# x* C0 Q2 ]; Udts0100630973    Problem with DxDataBook window when I change expedition project in to netlist
4 d4 u( ?: m/ L5 f- [7 x: h9 ~7 T' Kdts0100631052    viewdraw crashes when in a text being added to the schematic Unix like end of line characters are used (0A)
dts0100631270    I got error: "Can't open symbol definition for schematic block!"
2 p" B+ c- `- _, h/ z: ydts0100631630    I get Error: Schematic block 'Schematic1.1' has elements with duplicate IDs needed for Backup/Rollback and copying
dts0100631663    Renaming a hierarchical connector connected to a global net might create an invalid global net.
7 o! j. I# ]( m- S3 H2 p: T9 x) Z, R% ^9 adts0100631721    Navigator shows incorrect connections for hierarchical bus bundles
dts0100631730    Placing a composite with Add Nets and Add Net Names adds a net for a pin using bus bundle name.
dts0100631935    iCDB transaction rejected - project was reloaded when three users were pasting sheets at the same time
$ T& D  z% {! N8 T7 c2 P% ]dts0100631973    I get GPF when I choose Undo option
dts0100632623    New Project dialog -> Advanced does not set paths to the cns and cfg files.
dts0100632639    Rollback option does not work properly
dts0100632669    Rollback not save correct design state after backup fixed by DxDiagnostic schematic
dts0100632681    "Commit iCDB database transaction rejected" and eventually DxDesigner hangs when running packager and pasting sheet at the same time
dts0100632963    [Concurrent mode] DxDesigner crashed when first user was deleting some sheets and other user attempted to delete one sheet right after he opened the design
dts0100633301    Cannot package design just after migration - regression
8 h9 _, c& }: O  }$ e% Bdts0100633970    DxD Diagnostics reports connectivity errors after undoing nets renaming
dts0100634006    viewdraw crashes when exporting connectivity from ICT
5 S+ b8 T- y8 y/ R8 ~' F9 v' {dts0100634010    When viewdraw is restarted automatically via the crash handler ('Restart the application and open the recent project') it consumes 100% CPU and is unusable
dts0100634021    I get GPF when I choose Flip for ripper symbol
2 T" R; t5 @4 S2 Vdts0100634256    crash dialog has some issues on Windows XP Japanese
# m) F' _3 l/ D2 z4 |dts0100634305    Issues with a DxD Diagnostics 'Test: Top Level Name Consistency'
- r6 Z6 G1 M& E0 @5 M, t/ N. d7 Adts0100634332    Incorrect connections detected by DxD Diagnostics after copy-paste a schematic sheet
dts0100634819    I get DxDesigner is Offline mode when I connect symbol with nets
  d, P) v2 Y# }3 u' B- Zdts0100635233    DxD Diagnostics fails to fix 'Top Level Name Consistency' error in one pass
dts0100635581    DxDesigner crashed after nets deletion
* ^- ^$ k0 Z) q8 idts0100635605    I get GPF when I choose Mirror option
+ l+ `% }8 W6 k* c3 q! F9 }dts0100635619    I get GPF when I choose Flip option
' a+ }2 ?& M2 W( K9 Jdts0100635865    I get Error 1287: iCDB database update error: when I press Undo
dts0100635936    Problem with connection when I change size for bus
dts0100635972    viewdraw crashes when flipping a bus ripper
$ ?" b: q- |/ rdts0100636130    Japanese menu problem: RMB popup menu of component and Block.
- s# o1 K5 t! V0 _  q. ~1 ]dts0100636316    Propagate Properties Hierarchically locks all the project sheets (locks remains after it finishes)
dts0100636336    During copy paste scenario, creating new sheet creates it in the wrong schematic.
dts0100636675    I get Error 1287: iCDB database update error when I press Undo
dts0100569325    Copy sheet does not copy block hierarchy when copying constraints is turned off
- L) K6 \0 i) W6 B5 T9 ldts0100626105    DxDesigner does not undo and error message Error 1296: Duplicate IDs detected
dts0100635209    New DxDesigner Crash Catcher Dialog Details button should be removed
7 l1 h- \/ g8 z5 A3 i3 j( Edts0100634336    DxD crashes after replace when ODBC(Text, CSV) alias doesn't exists.
# A# S' S% Q! E- z# v3 Odts0100605359    HDL: the Unmap option sends vdel command
dts0100608880    HDL: Add zoom in/zoom out options to zoom inside the Waveform window
dts0100615226    Migrration on design with $ARRAY attribute stops without clear message what is wrong
dts0100615987    HDL: waveform stops displaying values after 100 ns
4 P: d! p& t2 \4 R/ q) j9 }dts0100617492    Using Builtin ports IN and OUT in schematic gets reversed in the generated VHDL code
" [& X5 F" `) V; A- I. H/ Mdts0100617927    HDL: the HDL Target Library for HDL Design can be set as the Modelsim system library
dts0100620510    HDL: cannot simulate configuration for attached design
' R" m5 g8 {8 E( {) J5 B& b, J7 h1 udts0100621591    HDL Simulation settings. ModelSim executable file should explicitely mention vsim.exe
dts0100621605    HDL: the path to the external text editor is truncated when it contains space
' O1 x$ e2 |. X! m% Ddts0100621903    Cumbersome handling of leaf components
7 i% i% l! b6 V3 Y- vdts0100622290    External Dx-ModelSim Flow: Unable to backannotate sim values into schematic
dts0100625569    HDL: problem with the path to hdl file attached to component
dts0100625915    Crash when setting the Modelsim executable folder
dts0100627635    Setting notepad++ as external text editor and then changing it causes runtime error
dts0100627645    Changing the default external text editor has no affect until DxDesigner is restarted
$ A& r; A. a, K5 {% l+ L/ R1 idts0100630111    Library is not shown in the HDL Libraries window when it has name with dash "-"
$ t1 |- h  j7 ~& jdts0100630591    HDL: signal names with signs ~, -, + and space are wrongly exported to vhdl/verilog
: x  N* ^5 @/ b2 c" bdts0100631341    Inclomplete simulation macro for Modelsim
dts0100633001    HDL files are duplicated in the Project Navigator - regression
dts0100634318    Cannot set simulation top level when using ModelSim 6.3a SE as internal simulator
dts0100635137    The HDL Search Paths entries are doubled each time I export vhd/verilog netlist
dts0100635583    Viewdraw crashes when editing hdl file, but the path to the external text editor is not filled
$ a5 E9 M" P. J+ J9 K; F" s4 qdts0100629187    DxDesigner Diagnostics does not fix the attached project.
dts0100632498    MGC_REMAP_RSCM does not work with server:port format
: i. N) ~) [7 a" x. Sdts0100620443    I get Error: (521) [Block fghf] Cannot change interface of symbol placed on schematic when I delete for block or net
! e  ]! g3 a4 d7 Edts0100625205    Reference designators for elements from fub in ICT, project explorer and Properties window are displayed incorrectly (U? R?)
dts0100629327    Constraints are lost after rollback in ICE based design
dts0100629380    File->Rollback removes a design from Navigator tree
* x4 t& n4 N+ u# fdts0100631286    Symbol Update -> Clear All Highlights does not seem to work in ICE documents
dts0100631297    RMB menu 'Symbol Update' does not work in ICE based netlist projects
dts0100631302    It is possible edit Read Only RB in ICE
dts0100592947    DA2DX did not rename the Supply Rename value
dts0100593885    DXD can not package if a hierarical symbol have vector pins nd the internal sheets have single ports for buss pins
4 }+ B" Z. M* v8 x' Adts0100600087    few DA hierarchal blocks are translated into Blocks but not into Designs level
3 V' ]" }6 H7 A, Gdts0100596003    DC2DA and DxDesigner need to support LineStyle6-LineStyle16 from Design Capture.
9 J: j% n# k# `5 X; P# Tdts0100630918    "Unable to open Central LIbrary" error message with the "Create local DxD symbols from DC schematic" option enabled
- [* L& q; t& S" O: K7 z" b( Adts0100631073    Translation from DC to DXD causes Duplicate IDs that cannot be repaired using DxDesigner Diagnostics
3 j( ?) r) P8 J6 U# T0 idts0100615611    OrCAD Schematic to DxDesigner 2007.5 Translator should have the option to set all colors to "automatic"
9 [9 _# V  T7 n' ^dts0100622712    The customer has an Orcad Capture schematic, which he converted to DxD. The schematics look fine, but when he generates the netlist and opens PADS Layout he finds a wrong connection (short-circuit).
, f2 ?" }: A* a3 ^! r+ }3 L7 \dts0100624063    Pin types migrated incorectly
4 @3 c$ o5 ]. }. v" V+ `/ Cdts0100625630    Unexpected fatal error occured when there is no path to file in Browse frame
dts0100632606    Specified file is corrupted or incorrect after import ffs file into DxDesigner using LineSimLink
/ x) P' a* b8 Fdts0100633786    Incorrect documentation - Importing from HyperLynx with LineSimLink
, h7 U0 g; [- R4 mdts0100619566    Export ccz - rotated properties are incorrectly exported
' X& B: c0 N7 s  ]" Edts0100619652    DxD Packager dialog has incorrect text
& {0 A- {; y. ?% F1 Rdts0100622705    Solaris - File->Export->Analog netlist does not work
: k5 u1 C, Y3 mdts0100624832    [Linux] Viewdraw crashes after Replace part when data source is ODBC compatible.
# _# K. B0 e, i" pdts0100624912    Add hierarchical property propagation script to the install
$ f# e! I; K; y2 pdts0100625050    Schematic sheet cannot be opened after updating EE2007.3 project to EE2007.5, EE2007.6 OR EE2007.7
- v- c% t2 T' x$ Pdts0100626477    <install_location>/2007.8EE/docs/data/DxWDIR.zip design not working
dts0100626672    pdbslot crashes DxDesigner
dts0100627156    IOD cannot create Design. vipc: Error 1347: Unable to connect to VNSD in vipcInit()
dts0100629663    Crash after double-click on schematic component in Variant View.
dts0100630994    "Cannot generate Schematic view. Finish or cancel previous operation" message from VM when reuse block is included in Schematic
: R  x4 U$ W5 K% q) l8 Ndts0100632331    Rename "Propagate Hierarchically" command into "Propagate Properties Hierarchically"
3 B5 A6 x. s3 P: ], @# n& Xdts0100632334    Change default properties in Propagate Properties Hierarchically script
dts0100632337    Propagate properties Hierarchically icon is not available in the toolbar
dts0100632404    Duplicate IDs detected on opening th design. DxDesigner Diagnostics does not fix the problem permamently.
dts0100632710    Viewdraw crash when generating variant view
dts0100632857    Failed to package ICE design.
dts0100632960    Crash on DxD exit when changes in VM Settings have been made.
5 Z$ P' C2 Q0 X4 n# w; Z! `; [dts0100634277    Packager does not package new components in migrated schematic
dts0100634650    Change default property names in prop_reuse_core.vbs script
dts0100634653    Rename command "Propagate Hierarchically" into Propagate Properties Hierarchically"
- v* \# @, V5 ?  ]dts0100635522    Remove Propagate Through Hierarchy command from Properties window
dts0100637029    Dx crashed when I ran Dx diagnostic checker and FA was runnnig
( y9 s, F/ C1 [1 `dts0100637288    I can't set PropThruHier and StopPropThruHier properties in the netlist project
; k$ V5 k$ }" @& l0 A! k5 T' \& xdts0100539584    Its not possible to rename the design name in the DXD Navigator (only 1 design)
dts0100625769    Navigator components do not match with page location
dts0100626019    Nets are visible in the Navigator window after unchecking 'display nets and buses'.
dts0100632951    Navigator shows wrong information after renaming a net
; C; t/ q  w+ i! C9 {! \4 x/ J/ b: sdts0100635134    Navigator shows an unnamed net after deleting a block
dts0100635587    Adding new sheet gives incorrect behaviours
dts0100635956    Navigator still shows connections after disconnecting a port
- G! z4 X& @& h: k) @dts0100605863    PCBFWD: Customer can not use Arguments in "Customize Tools Menu"
4 a2 K; K/ E* u: Y/ h4 F% V% h1 ~  Vdts0100625279    In this testcase (hierarchical ICE project) pcbfwd crashes.
dts0100630594    Please add PKG_GRP property to the netlist.prp file.
6 E; m3 u/ {/ f1 H2 Bdts0100630612    Add PKG_LOCK property to netlist.prp
dts0100631001    Wide pin swap does not work in DxDesigner <-> ExpeditionPCB netlist designs
7 o3 [7 H/ x( M* c$ gdts0100633309    The pcbfwd fails just after migration - regression
dts0100629388    Packager cannot package the new PADS Flow design.
dts0100626765    DxDiagnostic process takes too much time
dts0100615088    Japanese menu problem: "File -> Print" daialog has some issues of a Japanese translation.
$ l- Z& Y6 M! |dts0100632470    Altering size of print preview window causes navigation buttons to disappear
dts0100623059    Can not edit Instance Value in Properties Window
dts0100623081    Ref Designator value not visible in the Properties addin
dts0100625986    Project was reloaded and Error 1287: iCDB database update error: Invalid parameter was issued to Output dialog after a pipe character | was used in the net name
dts0100626286    Prioperties addin does not allow to use comma character needed to alias nets e.g. A|B,C
% V9 o( e/ w* L- j/ c  S! ?& Q; Hdts0100627194    Properties addin does not show net / instance names added by ICE (with $ character)
dts0100631681    [Linux, Solaris] Focus on wrong edit cell in the Properties
) f9 n' F$ j6 Q- W+ Edts0100631748    Properties addin does not show a name for a bus bit going through hierarchy
  ~7 P  z7 X/ v! fdts0100636993    Add NETNAME to Global Signal Name mapping in map.cfg file
8 c, G8 t/ H4 t: f* H* O& wdts0100620072    Place Reuse Block in Schematic Hangs DxDesigner
: ]/ }- _8 r# [2 c+ gdts0100625913    DxDesigner crashes after change to ICT schematic with Reuse Block
dts0100631979    Duplicate IDs detected after place very simple Logical OnlyReuse Block
dts0100633096    RF: Seg Vio when attempting to send schematic from AWR to DxD using the replace option.
" q8 f7 X; ?: g6 E* Ndts0100606970    CRM is leaving a net with MST topology but having from-tos
dts0100616398    Change page title from "New Objects" to "Text".
+ B4 h/ V2 @7 Y9 ?' a1 wdts0100616401    Rename Nets to Nets and Buses
" Y' u' l8 h( p3 i3 Hdts0100630588    I get File not found when I choose Settings for netlist project
dts0100634268    Strange chars in the settings for vhdl/verilog
dts0100495671    Strange rounding in millimeters
dts0100549052    Can not use Japanese font in Symbol Editor.
: m: o$ {% [# zdts0100631373    Unable to Save Symbol: Error UID Manager: Object not found
: L* V% w* Q2 [dts0100447920    Rules for Open Collector and Open Emitter always display error even if are used in good way
dts0100564958    VDRC does not create vdrc.log file if there is no "Log Files" folder i project directory.
/ s9 y9 S) t/ T: [$ Jdts0100575820    DRC-201 does not work correctly
dts0100615921    "Un-loaded net" does not work in the case of "PIN" type symbol.
# p- m' Y2 F* x" U3 }( g0 a5 ndts0100631988    Cross probing from a drc-103 opens a wrong sheet
dts0100635214    Connectivity warning drc-103 is displayed twice for bus members

careywang

多谢！

panadol

没有太大的更新哦！在功能上！

calvinxxw

$ p9 M( T2 @, N; y6 y1 N$ Q" z
2010/1/15 正式发布了9.1

biglin

Mentor不這樣怎麼搞錢.