cadence spb16.3正式发布了

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CADENCE SPB/OrCAD RELEASE 16.3 README --
Windows Version  
& m: }6 ?% Q2 X  W7 }Installation Guide  
You can find the Cadence SPB/OrCAD 16.3 Release Installation Guide for Windows, Version
16.3 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD.  
/ d: \3 ^, W# R; HMigration Information  
5 \0 Q6 X* j8 m4 _2 v% _Important migration information is contained in the Migration Guide for Allegro® Platform
Products Release 16.3, which is available when you install this software or on Cadence Online
: B- L2 E- h! {2 uSupport (http://support.cadence.com).

NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
. M# b8 \! t6 w. N' dSystem Requirements  
; ^' f' e3 O9 o. M+ y3 I7 xInformation about minimum and recommended system requirements can be found in the
/ m0 L$ I; L/ D. \Documents folder of the Disk 1 folder in the Allegro Platform System Requirements document
+ q; y# E7 s0 i& B(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com).  
6 i* v& h0 W+ Q( J/ v0 n+ U% A- J
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
1 D4 \* U( W+ l9 uare listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
What’s New  
Product release notes are available at:  
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi[/url]
ng/spb163/prodList.html
KPNS  
5 B5 c# J, F7 L( f5 D8 v, I5 WThe Known Problems and Solutions (KPNS) document is located at:  
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi[/url]
ng/spb163/kpnsList.html
Allegro® /SigXplorer® ABIML Libraries for Default Trace Models
3 n. [5 t7 [9 k$ S, C9 u- Z: vwith Surface Roughness Effect
The Allegro /SigXplorer ABIML Library is a free library that includes ABIML libraries for
SigXplorer default trace models with surface roughness effect. It is designed to provide accurate
) q, M8 }2 X7 x2 t2 `& utrace models in Allegro /SigXplorer without time consuming EMS2D solver runs. The libraries
can be found at:
http://www.cadence.com/products/pcb/pages/Downloads.aspx
This ABIML library is provided free of charge for use with Allegro and SigXplorer. The library
: T- L) T! M4 r6 ois provided as a zipped archive, with installation instructions included.
4 u1 m: D8 l' ]' s$ W$ U% fCustom Environments
) s7 y; J$ @& n* z$ BCustomers using custom batch files or scripts to set up their environments must add the following
/ o% f# [  ?4 {6 t! \: \to their path. There is the potential that some Allegro products may not launch without this
setting.
%CDSROOT%\OpenAccess\bin\win32\opt Downloading and installing SPB Software
0 O+ `# E) T# A# S3 O3 \Cadence software can be downloaded from:
http://downloads.cadence.com
9 |, M$ U  J; W. G" V5 k& O! T3 y
3 ]- g7 g/ J6 l1 [( ENOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software.
4 u2 v& e$ A: M# b) `. D/ yCadence Channel Partners are listed at:
http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
  f6 S6 A8 y3 A/ M* v2 D5 r8 H
; ?9 M2 z! g+ A1 \: c0 GDownload Disks 1 through 3 and then extract the zip files into a temporary directory such as
. V/ d2 \0 [  `. Gcdnstemp. This will leave you with a directory structure that looks like:  

Disk1 folder
Disk2 folder
! e3 O- |, _' R8 J) A& XDisk3 folder
1 b! I, v' O! sautorun.inf
7 D/ n$ [. z, [  F9 ]setup.exe
setup.ini
+ j* }3 |0 O6 Q" j% a! y1 o
3 y7 D6 G: T% D) m6 BComplete the installation by running setup.exe from the temporary directory or consult
7 K+ ?$ U5 a( b2 m4 @the installation guide for more detailed information.  

3 T' o$ j. }: i, R; t8 TWARNING: The installer will automatically add the programs in this release to the Windows
% p! S' R5 u- y- y9 NFirewall Exceptions list for Windows XP and Service Pack 2 at the end of the installation
6 {7 d" q2 h6 e3 y9 n; H. V% B/ Cprocess. If you do NOT want the installer to do this, you must run setup.exe from a DOS
! W/ P& I2 a" dcommand prompt window with the following switch:  

: v* _; y: E! U  rsetup.exe -nofirewallexceptions  

When the license manager installation is complete, continue by installing the Cadence
5 @8 @" V* ]2 U3 y9 zproducts.  
# [; v2 \# _# r7 \+ w" I
NOTE: If you are prompted to reboot, reboot the machine and log in with the administrator
6 P% s; O5 M: Q8 c# p1 h% Pprivileges login id to successfully complete the installation. List of Fixed CCRs  
8 Y; J) C. F/ r/ z% G+ J•  Enhancement CCRs
•  Bug CCRs
Enhancement CCRs:
& `  P6 ~; X4 \
: H3 v* |8 M3 v: m) QCCR ID  Description
7419  Customer menu options added to Allegro menus
8230  Use via in area constraint does not work
10658  Modify default formatting for Label texts and linewidths
0 M( U/ j# \7 ?4 c12216  Cannot set color or line width for wires on net-by net basis
13083  flip/mirror design to back side
13373  Select length of pin graphics
18072  Add docking option for probe cursor box.
21451  Change Probe print trace color yellow to alternate.
32798  pxllite complex hierarchy netname enhancement
" f$ p) d; E8 l7 e+ P$ r33896  Option for changing the PSpice probe cursor
9 ?4 X* Q3 n3 [) O39600  Option to see time spent on allegro database
' ~* \6 Y7 M7 _3 B; |4 A  y40754  Linux OS support for PSpice
8 t- W+ @5 }  @: g4 P60427  Add different subclasses for pin_number top and bottom
, u' {* T! }) B77555  Capability to export PSpice probe data points in csv format
- w  y6 V& G5 Z% A107219  Capture.ini switch is needed as a Registry entry like PSpice
132769  Footprint viewer in CIS should also show pad spacing info
, w3 c, h$ y4 u) F: _1 {4 L158838  Need easy way to delete marker
159977  need attribute mapping capability in mbs2lib and mbs2brd
162382  Enhance quickplace using schematic page from ORCAD
) c+ q9 b2 Y; b- z. r164790  Improve autorouting quality on diff pair w/match length rule
3 v  I5 ?6 `4 R$ D6 q+ x0 s* J205909  Constraint Manager displays in Allegro no graphic mode
: N# _3 Q" E* i7 t( A" ~6 w210027  Delete dynamic shape removes net name from copied vias
, r3 y( j- N$ n( O222127  PADS_IN: Constraints are not imported with the design.
: T0 n7 ?  A! T7 |( f8 ^3 _  J: L3 b236698  Report Unused parts in multiple parts package should be DRC
: ?5 i, _% }7 v' e" V( U" r4 T240525  Add ability to change cursor color in PSpice Probe window
1 q: u  Y/ J, d; r4 |  K245193  export dxf height information when blocks are unchecked
254183  Multithreading for DRC and CM analysis in Allegro
. R7 N: r- ?7 y282027  Problem with Split Part and part graphics
282507  request to import IBIS file directly
% n. j5 ?# r6 z% L& d283698  place by schematic page number window need enhancement
1 h: Y$ J4 V7 j( Z' d288540  Schematic page# display order request for Quick place
290283  PSpice - Probe - setting background color from UI
290641  Option to copy paste cursor value
298081  Models from Funtion.olb need more explanation
323813  Need negation and exclusion function in ADE reports
341484  Wirebond: Tools to generate wirebond manufacturing outputs
& w+ u7 t0 T- o( y$ ^4 f7 Q' c353212  Variant Name is not coming in Standard BOM
360602  Enhancement to Show element on a via
8 I6 m9 o! e  H( P. [362934  Enhancement for Allegro to utilize Dual Processors.
7 N- m" q: D7 g364850  change the font properties of Label Text
367468  Need a real DML_PATH environment variable
380714  Ability to have Power pin set to Not Connect
3 D( F9 g  V0 ]3 R: u. {382860  Display parts and nets in different colors
$ K( C9 O& i% U1 A384488  Add DEVICE and REFDES filter to Signal Model Browser
391487  Ability to have user defined directory for storing distribution files for MC analysis
420008  The renamed differential pair names are different in CM of ConceptHDL and CM of
Allegro.
420023  It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on
CM. 420648  Need to get RF Elements to retain previously entered values
429280  ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
, W( I  w# y, d3 Z2 E! y5 L$ `430549  GUI for ADRC XML Rule files
3 f3 P2 j: w( R430558  Store last used ADRC rule check ini and check values in .sip database
452606  Can we have last plot as a default  
454452  Allow neighboring/overlapping die pads on same net to go to same finger during wirebond
2 ^) [- S# J8 b/ y" W+ Hadd.
& a3 O, Z( c$ ~1 m* F% L456854  full AMS Simulator menu without pspice.ini in registry
+ v6 X9 d! ]$ E9 v6 q: Y6 z% ]464056  Setup option to always prompt to baseline a new part
; g. V/ r6 z0 k/ Q469378  Enhancement : Hide/Unhide feature for trace
475077  Schematic Generation Setup form is missing the Port symbol selection.  It was there in the
& [$ Z/ F1 a: L" y1 C4 S% `15.7 release.
- h$ ?, z! _  Y7 ]) x475714  User Guide should mention that Temp Sweep is not honored in AA Flow?
480843  Requesting ability to View > Zoom Mirror current view.
484632  Request for Bond finger to snap to Guide in Free placement of Bond pads
7 _4 m) s+ h1 Z) S7 N4 S" ]( T/ r490948  Provide a sketch line and text property form
500550  CRef's should be preserved with the next run of the schgen in the preserve mode.
505284  Enhance The ConceptHDL can set the color for $XR0 property.
* v: ^% p1 ?' o7 ^2 V8 N8 D1 [, @. t512748  improving arc routing
) r. X) J$ A7 T" k/ v. ?, J  p- W513967  staggered C-line via arrays
& N$ q1 Z. w; g5 @% r515333  Option to specify spacing between Components in the Generated Schematic
524924  Add PSpice enabled part gnd to standard library folder
525748  Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
526818  Retain Hard Packaging Information option does not work for SECs.
528391  SigXplorer measurement is wrong
533844  Allegro password not encrypted in the .brd file.
( {' y, u/ Z+ x" r536681  In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge
Spacing
7 _. p$ Y7 t: _! }4 n: H536948  Allow  sorting of power symbols
8 z% l, ?2 k$ c* D* i539407  In ADRC Minimum Shape Check requesting individual "Layer" option
- b2 y7 j. U8 Y3 ]) E5 I541145  slide command does not support to keeping the existing arc
541214  about supporting OpenDrain Model in Quad2signoise
542414  A function to force diff pair spacing to primary gap.
; |# K' _  a; }) l+ ~" `542803  A "Minimum Shape Check Soldermask" entry is needed in ADRC
543470  Provide rectangle and line width thickness for Drill legend in NC drill Param
543766  Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks
545408  Cursors are toggled off when deleting a plot
% s6 y" c# l. }# F  i546891  Enhancement: message improvement when expand design action in Concept
. m. R% E' k5 f6 n: x546985  XOR function to allow to compare layers within different or same designs
7 p% R! [8 Q# s- b1 a548920  Add a document of which properties can be synced and which cannot be and the files
required
553669  Add a 3D viewer to Allegro
1 G7 Q* Z/ G: ?  [6 J; F555183  Wire Bond Report --- Report field should have save function for reuse
3 }# U, I$ b. q$ V* v" J556200  Need listing of DE HDL command names and switches.
9 J; \/ U5 ?; a6 O! t' d$ y/ ^556883  Grid point for Origin to be highlighted
% ?8 X3 @9 g; b7 l559638  Enhancement for importing height from PADS in allegro
/ Z; o: T  v7 |8 W+ g$ e559724  Request cline via arrays to be applied to diffpair nets
& ]; j  N( m: g' A/ ]; |& N560134  Show Element Customized Display
) l( R4 H% w* I' f9 t563957  Enhance Color Dialog form Class/Subclass section to expand vertically when the form size
increases.
  ~4 V- Q6 h# V* @5 J! L568058  Request to have component information available through the context menus
568273  documentation of variables in Capture.ini
/ t- V" @- u: q% J569615  Enhancement to import constraints from Mentor Board Station to Allegro PCB
: x6 S1 b3 k2 |& L2 R( `6 j569680  BOMHDL defaults to the wrong file type when html report type is selected
569784  Request ability to assign netname to via during copy
569863  User would like to set a larger default trace width
570128  Enhancement : Packager setup for subdesign drop down
' O8 ?. C8 W( }% \6 m570195  SiP - Provide option to create/combine BF labeling with additional text required for Bond
& v  ]+ V  H$ x- J; s; Fdiagrams 570861  Unconnected mark does not be removed even after wire is connected to the pin.
575211  Web links in CIS explorer are not working when Firefox 3 as a default Browser
577944  Enhancement request to have the drill legend for thru holes and slots to be separated without
being on top of each other
: h0 X( P7 P8 L9 L5 E583630  Can Multiple Section pop up box be disabled?
583712  Ability to have string values for SCHEMATIC_GROUP property
585904  Find a schematic page with help of nets
8 c# L) \# ?; R7 U: K7 S  i  a589316  Document change in Gaussian distribution for PSpice MC from 3 sigma to 1 sigma
589512  RF component snap is 'too clever'
590246  CIS to Allegro flow to include or ignore constraints same as HDL to Allegro
  i+ @1 B# `1 W+ L; B591306  Suppress RF edit window when changing RF Element properties
591318  Use RF setup values or retain changed values in RF Element forms
591443  Temporary highlighting is lost when using the Copy command
591450  Provide a dynamic tapering option to RF PCB Route
591489  Would like to suppress RF Snap windowing around the user pick automatically
* W' ]6 b; Z. s/ U9 Z591812  Provide move options for the RF Snap command
591817  Provide easy group and element ID in repackage form
591825  Quickplace for RF Elements
591865  Request for more information on 'Other' Netlist formats
! z2 l. j: q$ h) V) T$ K  x596392  Publish PDF needs improved error messages for missing installation.
3 `& M7 b5 b: `! V$ X596555  Request alias symbols documentation to include and clarify when necessary to rotate 180
degrees
% O8 t. `8 \4 W& }/ p) Z596843  Cannot do global search after importing read-only schematic block
597808  Option to increase the default thickness of all traces in Probe
599499  Plotting from within Allegro does not find path to stipple file
604125  Manufacture>Create Bond finger Soldermask.
605023  Need rats by layer function for Free Viewer
; P: S6 ]1 @; h% w3 S# w4 \605112  Dies should not be counted as conductor layers in Design Summary Report of SiP
; P- _' f5 e' F/ g3 e605373  importing and Exporting BondWires
609035  Voltage_bus part - Make pin number invisible
2 g# g2 |! ^- k% g609561  Enhance Circuit Replicate to support coppers shapes connect lines and vias
610934  Retain user input values in RF PCB forms
3 z; O8 H2 W7 S9 x612008  Mirror Rules need to be documented for axlTransformObject.
613639  Update Documentation for "split_inst_name" property.
2 r/ v2 c; C" k" z614345  Email facility for Design partition on Solaris does not work
* E# L3 ]7 n; I. z+ I& E$ [615139  option DMFACTOR  documentation missing in pspcref.pdf
615374  Retain Soldermask Thickness value in 3D Viewer Options
1 w  H( \) t9 Y2 [7 B3 ]1 H615850  Auto Setup should honor device setup parameters if component value is null
615988  PDV WHen importing from Mentor does the browser not remember the last location of
import
# e% l: Z. v& y- @1 ^8 a4 D616529  15.7 Design Entry HDL fails with Out of Memory message
616873  Uppercase characters in design name error should be improved
617976  Enhancement for a way to sort user subclass in define subclass form
620289  Server 2003 support information in pcbsystemreqs.pdf
, B8 w# t; A" t2 {620303  Enhancement: Shortcut key for "Select Entire Net"
621054  Renamed net in netlist isolates components from the rest of the net.
621955  Offset Via Generator utility should show a warning message if vias are already present.
622203  Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar
3 M4 F8 k$ M! w/ ycommands
% |. r+ {6 m# }' L- M623218  display pin names associated with a net in net Properties
623908  Mirror Symbols while dynamically moving enhancement
624817  Display padstack name in data tips when hovering over Pad-stack
3 \; C4 a0 G* H, ^# s( Y$ t625733  In Netlist Report they are requesting square bracket vs angle bracket
626605  Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB
( b1 [  d: Z3 R5 Z3 RXL and PCB GXL
626673  16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows
rotation and allows move but
1 k: G9 o/ i" T3 n2 T( P& L; f629008  enhancements for find command
629548  Request an Option in Create Plating Bar where it may be directed to a different Subclass 630949  DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire
profile"
# m6 g# {0 {/ f/ o* h" t4 s4 R630955  SCM does not see design difference after update of fixed die/BGA in cdnsip
* ?. z% B8 N# a, y630973  SCM should see the net assignment made in CDNSIP for Power and Ground pins
631609  Clarify how to generate a cref.dat file in Cadence Help
631697  Want to degass many shapes in succession with custom parameters
( w0 S2 n: l4 ?632754  pspPN and lib_list should reflect location of new models in 16.2
633440  Sensitivity not varying components correctly
! \; x$ P+ M& \4 d! F* u7 }" j, Q633842  Add note to docs regarding padstack quickview
634350  Enhancement suggestions for pop up info boxes.
634877  Export netlist with properties changes scope from global to local
635118  SKILL variable to obtain list of Classes and user defined subclasses in a database
* z( c5 Z' {' U" R2 \635233  Place hierarchical pin tool tip
7 @' m+ J# ~: t! K+ R4 a635543  Any command to get the current line/lock type information?
% L6 l5 t; @) L; u/ B: m635579  Enhancement for Structured format in parameter file
636930  Die Export option to create symbol either from schematic or layout
; b! \, T0 ~$ ?637195  Allow for SKill access to backdrill info on padstacks
$ ~7 M! B, U5 Y2 a637768  Enhancement to assign different colors to different net based on a unique property
638455  Enhancement: Add some details regarding nomd.lib
; s( v% m8 d& K9 X638581  ENH - Press ESC button Spreadsheet window disappear
$ L7 D& F& k' k, }$ l( H0 R8 s1 E638622  Add note to CM Spacing Domain Region worksheets regarding shape2element clearance
638910  Enhancement to sort the list of available vias alphabetically in the via list ?
639630  Does the Net_Short property work with Modules?
& A# B9 Y  V, q4 m5 x7 G640262  Request object membership count in the status line and forms of CM.
+ s% O) Y7 \2 k0 Z* Q  q8 I1 d640280  Provide resizable windows in CM and other apps
& L$ z* m- C$ P! a" K640668  File>Change Editor needs ability to go from GXL to Performance L or Design L.
642095  Ability to disable the Pop-Up description of elements
+ \1 y: x: |  I4 n% y2 R7 M: Z642298  ENH: For license checkout detailed message
$ P4 R0 c) _! [  t* L3 {642422  After Copy parameters from one part to other in partmanager forgets previously highlighted
line
642865  Allow format of hyperlinks in ptf files
5 m+ Y: M6 E' T' J642894  ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help
643381  Add an option to ts2dml to allow user specified port ordering.
8 q# H6 Y; c5 n* G8 ^9 d  M643390  Request for a switch or button that would allow Properties to be maintained during a shape
merge
1 n: d  I* l5 m! o, \643625  Bond Wire export to DXF does not support WYSWYG
643790  Include Associated Components in the Verilog netlist
0 r: {, s; d+ q8 w, x* L644216  Store Filter Row Data and Units Of Measurement in site-specific file.
: N6 }- I/ `$ J! w9 w4 e; @. b$ ~644248  Need a better solution to identify and handle unstuffed components
# T& I( j: L# b644350  Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
* x0 |3 e# |; a6 X% N646662  Enhancement to add feature to toggle on/off inter communication tool from within PCB
Editor when using DE CIS.
! }' Z+ t0 @) |3 O, S' f7 h646981  about the treatment of NO_GLOSS property in Missing Fillets Report
  W: B: q, o' o  {+ y647480  global setting for adrc settings in sip via techfile
647617  Degassing not suppressing shapes less than size specified
648210  Request for Working Layer (WL) model in all tier Allegro tools..
648218  must delete keyword "multiwire" from Doc
648533  The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented
648801  Stream Out issue for SPACER
8 z/ R- Y6 I  p648930  If two PPT option set names match a given component which one will be used?
3 x( l7 ^  L2 b0 n% o649603  about spara import
649607  Management of SiP Technology File and Project Information
1 ?0 Q5 H" U# t9 ^! }* E* ^649610  Management of Part Table (PTF) Files
7 y$ @# p! V  K, [  O0 Z0 K. l* p649613  Management of Library Lists
651684  documentation improvement request on cross-probing in Capture to Allegro to Constraint
Manager
652335  Tooltips clutter Place Part dialog.Option to switch it OF and ON
9 ]: q+ T3 f- ]652511  Unplace Component command
! c4 s  r! H6 E9 h4 ~! g# @652547  Description of ForceDBArg1 should be added  to PSpice Users guide 652554  Enhancement request for Allegro to check the vias used to the allowable vias defined in
constraint manager
' A/ B. V) ?) m" j! a4 F: B652939  Is there a way to predefine the values for Sample Start Height and Sample Start Length in
Wire Profile Editor?
653027  Explicit RMB "Done" option is required in Part Developer symbol editor when editing text
& o; u$ t  C8 D  ?/ _653359  Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using
& N) e3 L! P" Bthe section command
. p0 A% e; l( }653420  Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined
minimum constraint value
653471  Request for Die Text In Wizard option to Flip the DIE coordinates
653825  sigxp_tier was not reset when installing a new product suite
653902  Enhancement: Print Option? setting in Capture.ini file
657180  Enhancement: Tooltip for DRC markers
657187  SI model delete enhancement
657189  SI Model assign enhancement #2
657501  Negative planes doesn't match with Film View
659543  Need a Report to show which Die Pins have no bond wire attached
6 B2 \) g. w5 V- V. E8 {8 p' S659661  Function needs for setting the rotation angle in finger by group.
661477  Color192 window sections to be resizable
. ]4 ?( \' v4 M5 X& r662215  Please add the function of renaming net by batch command.
5 B; n5 U1 J/ a: ~662325  Skill code example axlDBGetProperties.txt not correct
662982  When you edit shape, ministat should always enable shape
663260  Enhancement: ALG0051 message should be more specific
663754  Enhancement to create Device file when saving dra file on opening another design
664240  Add CNVPATH in User Preferences to place default CNV files
0 h& S" N' J' m0 Z& H665798  163BETA - provide graphical examples to show result of Flexible Shape Editor actions
666186  Enhancement FishEye functionality in Variant View Mode
666768  Temporary graphics for modules / groups do not reflect true size
2 [6 l" W5 C3 E, d& o) ^6 \666775  Update microvia to microvia DRC markings to avoid upper and lower case confusion
% G+ s1 p1 N6 Z: G% J' i7 a667773  Request for ability to set grid definition by entering simple formula
* m) ~' N& K; y8 O+ U668110  Customer wants to enter the value of radius when editing routes.
& b; \+ V: M2 {5 h. {669373  Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
669380  Add options for ts2dml in MI
669798  Add all 5  Dyn_Thermal_Con_Type property options to Via_Array.
670775  Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
* w! w3 S% f/ o8 C671194  Allegro not to crash when opening unsupported files
: e$ E( i  K3 Q  e671337  Request performance improvement to access DML libraries from SigXplorer or PCB SI.
7 j: S; Y) W  Z2 ?, t671757  Handling of double quotes in HSPICE subckt.
4 r' H8 Z$ B  _( B672930  ERROR [DRC0039] Tap may not be connected with the bus Check Entire net
% m- r* e: {! w$ n2 a674666  Report the wirebonds XY coordinates
675118  Cline change width command enhancement
675151  Insert comment option for database elements
- I' _. A2 h+ G: c: I: b1 @675398  RF PCB setup should automatically point at the project file if Allegro is launched form a
  ?2 Q% Y* q1 @4 ^1 Eproject manager
2 i8 r  a. X* k, H/ |  f/ ]675551  schematic to sip layout fail
  E7 H+ g: k; D5 B676814  Signal Library command with Allegro performance license.
7 z5 U, V( a8 _" t) m* z& J( _; A676906  Add switch -regenerate_xnets to the dbdoctor dUI
677983  about setting of ibis2signoise option "-d" as default
) N, r% n% c" C5 {: _678036  Request for a Physical design compare.
678798  Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
4 ?" W) h) G. j0 E) @679926  Testprep fails with no route keepin. Message in testprep.log ambigious at best
4 R) L) p( t) v1 ~) \680586  Explanation of functions and macros in online help
6 @% X, F4 u3 R/ d% S! A- j682098  Color, font, Text Label in PSpice Probe Window
7 m- C* j6 N% l( N4 M682695  Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs
rephrased
682865  When using PTC format IDF files don't use forward slashes.
684409  Add info for non availability of SIGXP on OrCAD Demo version
8 r- Z1 i9 W, ~  r% G684713  pin_count view needed for packages
684796  do not delete all vias with DRC for via array 686103  Replace vias evenly spaced apart
! ?5 Q+ {' q+ R- n& _$ \" R; Q686112  Add Connect and Slide keeps cline length
686122  Select objects by polygon
687155  License for batch signoise command
/ N2 q& Q6 A0 @8 B* ]& L687187  BGA Full stagger matrix wizard generation
* _4 @4 s( p: X  S1 l$ z3 ]% [* j687201  Improvement in Find feature
+ V+ w% [4 q; l2 w687685  Documentation of new properties in Variables block
688047  Include blank space in pin name as the illegal character in PDV user guide
688830  renaming feature discrete library translator
/ ~, G9 c- j3 |+ \9 y2 C' Z689720  Need the ability to re-center Vis's in center of Pins when a Die is changed.
5 s( j! x) y  H% x: p695957  master.tag generated from the table design needs to contain the verilog representation of the
sch.
0 _" w& ^" Y7 q3 l' _, Z; W696661  Add ability in Offset Via Generator to add vias per a given Net
$ y- I2 K* g  m" O, t0 P" G696812  provide description for axlCnsPurgeAll() skill function in doc
697824  Components not installed of variant design should not be extracted into SigXplorer.
1 @# F) W9 f6 @  ]! L4 ?698097  Color Dialog form (color192) does not resize correctly
700262  Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the
Allegro PCB SI -L tool)
700712  Defined pin locations are not used when using Die Text-in Wizard with default option
Center pins on symbol origin
) a( f& m! Z% j* O: d701514  axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"
1 v  e! c9 K) g701810  Document what all database sources are supported by Capture CIS
702190  Request support of Windows 2008 Server Editions.
702613  Request SaveRefdesModelAssignments support the include original model path option.
8 K7 x, A& R$ N- w4 J0 k: y: L9 G703905  Need Hot Fix number Info on Help >> About
704594  Update symbol removes the text present on Package_Geometry/Silkscreen
704899  Split Bundle Methodology Should Include a Next Function
- O: O2 U4 \" w! b6 C704904  via matrix should be available in Allegro L and OrCAD PCB Designer
705601  Please make listnindex a public Skill command
705615  During Updating Symbol the text location and size are changed so Reset Text location is
confusing
% ^& j$ s8 Z3 [3 [, c( j706165  idf import fails to expand drawing enough to accept text.
706457  Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
- a  k: }. c& _- }5 a7 o706463  Add optional Character in the starting of each line of the file created by axlLogHeader
* K, l8 X: o2 ]0 H; d3 D706787  Fillet should remain when user slide the segment far from pin/via.
* [" r  Z2 J1 m" p$ f709119  Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via
Generator
: M3 D8 ?7 o( D711837  remove the comma from the image of grid value separator
8 |0 @: a* e/ N- ~714840  Enhancement: Anti-etch can be recognized as Void element.
. m2 n0 t( V4 W715454  Option to configure Design Entry HDL for Cadence Help
/ E8 N" o- I, q6 N$ O( c) P+ U% o715713  Enhancement for Wire Short Check during move feature
" Y4 a9 |* \! l8 O9 b7 |716671  About the log file of the na2 interface.
717722  Pad designer  File > save as should have recent file name in file field
) Z. d2 z5 V7 {9 ?5 U# J/ Y! e5 E5 r" y718431  Enhancement request to have DRC checks on negative layers.
719050  Log file should contain username date and time while creating or saving .DRA file
719514  Request length column be added to the Dangling Line Report
720297  about "rip up thermal-relief clines"
722346  DRC checks for mismatches in labeling Net
723661  Add *.pad in the File of type drop down menu when executing QVUpdate
" }  m  q5 @, w" I+ i4 S! s$ k% }1 }- L724832  Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 -
nil)
* b' P; ]) f8 u3 M, l' `# z726057  Request incremental DRC update when enabling DFA constraints.
728908  Add Color View Save and Load in Symbol Editor
: w: E  Z0 e6 I; P7 y1 z9 @729947  User would like a metal usage report
# _# f/ M& d. L: D$ e7 a; B
# x0 M9 z3 q% I" S+ l

) p" P/ P3 b0 V" P5 ?5 s Bug CCRs:

/ b- B0 c2 p+ C6 o0 Q. eCCR ID  Description
' E9 B5 z# H; d  S, L7 u4 A& l  t10116  Add Intersheet references does not work in Complex Hierarchy
11833  Junction not automatically placed when it should be.
' y: z2 D# i, y, {! z, r16310  Simple hierarchy, intersheet refs not refering to H-block
5 D  E/ W7 F' k! T& ?. _19343  Request for intersheet reference to show grid reference zone
22424  Intersheet refs wont work on imported off-page connectors
5 {/ M' ?. u4 O! n' s34275  Ibis2signoise fails with legal characters in file
85735  Cref annotations of the P_ID+00 Bus were missing
: J( z. j9 L5 h# X118279  PSpice command line options problem
134692  DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
" B% U: A  _& U4 z0 M' e. m! {0 @136260  Problem with netlisting the design in PSpice
199343  Stackup-Aware SigXplorer
3 r: I3 R9 t& W3 Z/ |207620  Part in MISC2.OLB has incorrect pin out
270347  Changes to AXL SKILL must be Documented.
283839  lm117 dropout voltage is too large
296826  Variant view displays library property
! v% D& Z. Q( `( D299384  Part rotation resets the text to default position
0 h2 k( `/ o5 Y5 X328647  Replace Cache takes time for network libraries
9 }5 \7 I) k; R. f- d+ K) d340323  Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
, Z7 ]+ n4 T0 i7 Y; ?( t0 ^3 A341035  Dynamic shape fails to fill in design that has cline arcs
9 o: M4 M) g4 _8 z7 \390692  Via not getting transferred through the Area Constraint from Allegro to Specctra
! Z; X# |( T7 k8 f" n! W; A( V405611  Environment variable for SIGNAL_INSTALL_DIR is resolved.
$ _0 o1 c( e" ?8 j6 ]( u428261  spaces at end of pin name Could not create new pin inst library correction utility
436908  The color dialog window will loose the vertical scroll bar after being minimized.
437369  Menu selection of Export > Libraries fails to issue the dlib command.
462783  Busname is too long
495671  Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE
. Q- b' \; L- Q" z) bProps.
% O* b& @% Q5 ^2 w# t; O' j: T8 q509393  NC drill legend copies null nc_param.txt to current dir.
512809  Window Prt.part.ptf shrinks by 30% and I have to maximize it.
/ n1 e% G" f" D2 O* ]520802  Global Navigate Zoom to Object needs to remember last setting
528686  During text edit the cursor overlaps a letter rather than in between
531555  The diode BAV99 from library works inverted in compare with the graphical
representation.
' ^% l  B* O" z4 l" a" _532603  Specifying TC1 and TC2 properties does not seem to have effect
547339  CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor
548143  Dynamic shape on Etch TOP will not void properly.
550657  Importing registries do not setup printers from MWcontrol
552227  about die export padstack  layer mapping
% D7 p7 ]; E2 o6 F9 t3 ~553035  Cref Synonym and Netsbypage reports do not match netlist
6 `9 s9 l9 e# u2 A4 C557660  Incorrect value for I_sinusoidal of pspice_elem
: Q7 Z. \6 _$ `; V7 E: M558164  All variants are affected by function regardless of being called for
558692  Memory leak problem in loading marker files
565681  Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it
$ J- Z( T3 h3 `+ C" Zshould.
9 c; h- n" d0 L- c7 [6 E567606  PDV selecting pins in symbol editor shows pins off grid during move
  `: q4 u, h* Q8 P" f( X568049  Genview crashes
. E! r9 ]1 x0 R575353  Large box displayed with place manual-h and no RefDes variable set
( c2 p5 Z5 ?+ ]5 x' K581848  not able to edit Padstack Boundary
! Q" F6 P- D$ |2 m2 f0 r  v* M( q591847  Add Intersheet References does not work on simple H design.
: v6 Z2 F+ d* c& U! p& w( r+ r592381  Physical Min/Max line width values not check on internal rows or forms.
593076  Cannot redisplay an invisible OFFPAGE connector's name
( u' M  Z  i' f5 U, ]* A: o598038  Detail button of Markers window with 16.01
600967  wrong order of nodes in PSpiceTemplate for part AD8138/AD
601415  Allegro Design Entry Tutorial corrections.
' K6 J( r. K6 u+ Y5 E9 ?. N5 P% z601531  When using the place manual command and rotating part a ghost image is left behind 603181  Formula to calculate the Actual Temperature for Smoke is incorrect.
8 J- ~9 w# [/ ^' O% t. Z604965  need to document how tcl cmd addComponent handles property values with spaces
605843  Aliased nets do not fully dehighlight when next net is highlighted
606493  Targeted nets are not remaining targets
/ R& v% r! T% b/ ~; L  A608150  TestPrep generation is creating DRC errors
" H. ]# E7 ^! w: M( R608787  Missing Constraints Report
: W% o3 U5 [4 U- b7 u2 P608942  PDF Publisher output misaligns text in tables
612511  Error in Flow Tutorial regarding checking default user units
/ s/ j& M; Z- N612982  VLIM model giving error that line is too long
613194  Adding wire bonds with current selection does not yield DRC's, mismatching Allow
, x! J' F! @! y* `8 y0 B& }DRC violations option.
' R6 j& x) |6 p. d& ]3 A* n613738  Variant BOM report lists identical parts in separate lines due to POWER_GROUP
) l; y* n. U7 ?5 K5 i* `2 _0 r617146  Symbol fails to place through Component Browser
% g% P5 P9 ]" I2 I4 G) v( \617327  Change root operation results in SCM crash
" n+ B0 D& j3 S5 z617784  Trying to open page 2 of the design Capture crashes
0 b9 x. o( u& T# D" ^9 N7 P. {618150  Property Editor Functionality
618617  Enabling strokes requires checking/unchecking options boxes
8 J. @: p) A( d, V# R8 Y618771  PDV error SPLBPD-382 when importing from APD.
619053  Diff Pair problem with creating them in DEHDL.
! y4 ^) P( k1 @- ^619849  Hierarchical Blocks Loosing reference
# H7 V$ s2 N3 K3 G6 x# O9 N* J620001  Measurement's Maximum range calculation is not correct
620343  Bogus error during schematic write
620826  Changing the units of dimensions does not work
621072  Capture CIS Crash while configuring Database
6 y$ ^- H' p6 ?3 ^( c- r* g+ C, h; {" l2 G621163  Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire
to bondfinger optical short
  z2 x( o0 N7 b3 h622263  Drill Customization sort order for oval oblong slots should account for Size Y
622583  Allegro produces erroneous error msg - symbol not found when the placebound is too
large for the board.
! `- E9 `3 j2 u; J# }' B  p622692  Why is VGSR negative for N-channel MOSFETs
624378  Device file content conflict
7 Q# F1 N; N, {, p624492  Model Editor finds the wrong model definition for BAV99
625462  Symbol pins Property are lost when once stretched
" W/ J& i7 [' o5 @' z( |+ T8 y625519  hspice_mt is not used in Channel Analysis simulation
7 g- z, Q) N" Q# D9 M0 y, C% I626674  Allegro CDS_SITE setting don't appear to match documentation
0 ]: X. ^8 E4 r* F4 N  s, I627018  Find Net in instance mode displays twice
6 n" A% |) ~4 n! j4 Q- @' x627864  EDIF c2esch crashes
* Q) N9 i9 i- R# Z, A8 k628077  Degas not voiding correctly
0 X" O. i; e* n* p5 q/ q4 b628265  no "Unused Blind/Buried Via"Report in APD products
628845  Markers> Packager menu is unselectable even after pxl.mkr is created.
631344  Mouse Wheel Scroll misses the "along with the Control Button"
* [. ^4 _& ]+ e& I' {+ J, t% }0 a631792  Design Compare not working for OrCAD PCB Designer.
' e8 c$ |1 o9 Q; U9 O631910  Capture hangs when working with search option
8 [. N3 Z  z( g633084  controlfile for OrCAD installation does not work with PO100E and PO200E
4 [, k6 C+ E; A- b633086  Generate Part for Pspice Model is incorrect
633130  The Verilog netlis is wrong
633223  Running skill from a HDL script causes segmentation fault.
& {1 B7 v& X& a6 e" r' x633473  INPUT_SCRIPT inconsistency when removed from .cpm file
) V) v4 _- N' v634075  draw_etch_outline doesn't work for circular shape/arcs
635779  Allegro OpenGL distorting text at certain zoom levels
636156  Unable to convert SDT Schematic to Capture Design
$ `+ j4 a$ w. U3 l$ f$ X0 e636215  Allegro documentation for Export Parameters is incorrect
0 h: B" T" Y" C) H0 j+ k. u3 S8 m636585  Rotating components in Capture reset property position
1 v5 a. S8 r' H5 g: r636688  Signal Model Assignment UI and Find filter association is broken
& @( S: c" W9 W. i8 \, X" a636819  Documentation wrongly indicates that DFA Analysis in unavailable in XL
637379  No column for ROOM shown in Constraint Manager
638140  Intersheet References not offsetting relative to Port
% C1 ?3 M; `& K$ B8 X638670  Testprep parameters - padstack selections - Bottom Side replacement text not entirely
visible. 638987  Change command hangs on customer?s database
639052  Database Objects Preventing Layer From Being Deleted report fails to run
: l; r& b8 P% H" P+ N& |& l; K639685  Capture crash while deleting a Hierarchical Port from the Design
4 A' o; H: C- q* ^9 s639698  HOME variable defined with %USERNAME% doesn't use value of variable.
5 F# ?( n+ U8 d7 f639829  After setting Zoom key(F10) to a new alias Tool Tip is missing the key number
2 p! E; |& Y, s1 r2 j( B( ?! B640127  Correct IDF documentation regarding UNOWNED objects
" s% I4 @6 `9 F640293  performance issues with scm and large pin count devices
640314  The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
) N: I( n# m' s9 a641503  Stop running the VAN check on a PLUMBING body symbol in PDV
) Y+ D3 a  A) N7 F* z641676  Incorrect link to assign refdes help
5 a9 y& [# @; e7 ?5 o" H642053  Drag Connected Objects icon is always display as on
642299  Switch the windows mode by set command
& A' S3 P) w) J2 Z. Q( Y* p642436  Save As symbol in part editor is not working fine
642713  Materials are not refreshed when material name have only numbers.
642873  Dynamic shapes out of date message refers to Setup Drawing Options
* [4 F! k& G; }8 v, K; L- H! i4 |643721  Attributes with Null values in symbol.css files are removed when saved in PDV
9 h5 C( a  q5 j0 B7 y643949  Can not create Region-Class-Class for same net class.
644016  APD crashes when creating a tile from LEF file
644733  Import reference text file gives incorrect results
7 [: ^( b4 V3 O9 ?7 O( e2 j644879  Change forms to enforce naming of lib.defs file
4 N7 V0 F" g) t$ T3 W# U- P/ K645046  SG1525A PWM model is reporting unmodel pins and producing incorrect results
645427  The save button is not enabled on changing the line width
+ l4 p1 M. ^) _' B* o645996  con2con fails to parse ppt file correctly
646175  Please modify the limit length of "Allegro PCB Editor Limits" correctly.
! k% ^. u) T% O7 b2 V647555  Drill Customization text Non-standard Drill is not readable.
647628  Annotate Type should be removed from PPT Option set files and documentation
648443  Launching SCM without a license is not reported in debug.log
, {( F8 F) ~+ Y. [649166  Capture CIS crashes doing Place Database Part with non-admin User rights
649222  Silent install adds extra License Server to CDS_LIC_FILE on the client
1 f, J3 {& G* u( E$ j7 c649570  PSpice COM Wrapper error while opening Capture PSpice project.
& x; [% K% \0 c/ y' O$ z+ {) }650558  Die Pad layer changed after refresh padstack
4 {1 F2 p1 D9 w2 {3 o( N  @: v0 a) x650997  Incorrect Pin Shape in CIS Explorer Footprint window
6 E+ x' P: ~/ ?6 i651000  "Wire length over parent die" violation is incorrect.
: \5 z, D' C# t4 n2 N& ]651153  Results for imported CSV inconsistent in PDV
651521  Resizing the display color visibility dialog box corrupts the display
651526  Parts are missing in a advance analysis library list document and font size issue
5 X) b! k: a% _! K& j' \651532  Scroll bars disappear after minimizing the color visibility form
9 L4 P1 u, m2 R( y, S: j652050  Append waveform does not work in 16.2 for .dat files created in previous release with
import text format
; X3 x+ v& l" f0 j7 h; q% x! u652904  significantly low performance issues when using edit interface to delete ports of block
653067  Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?
653784  Off-page connector name change to internal starting like "I12345555"
) q$ O; R# V+ ~0 }9 c* i; r$ o654580  Save As should update lib.defs without executing the edit die operation
- J" @8 s5 o2 d7 s8 ]* T+ t656282  BGA Generator adds outline and RefDes to wrong subclass
656723  visibility of clines in 3d viewer needs ALL instead of just CON field in layers
$ p$ _9 D# ~; J" J& W  Y. T657836  Text crop on User Preferences Editor form
1 {3 f7 [( w  N" V658347  Rule Continuous Soldermask Coverage Check should not work on Cline Segments
659437  Move group fails to display anything with Open GL enabled.
) U2 k. R- a0 c# C" [) ]. u$ M660937  Import techfile fails with etch on layer yet layer has no etch
' S9 T  I3 A! k4 t! q( A% m661369  Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
, r: c* a5 x/ B+ U& `+ N" c0 l# i661754  Hyperlink publish pdf to correct page but wrong grid location
662622  Export Physical reports error Output Layout Filename contains space
662918  Skill code example for axlReportRegister does not work
662971  Moving Bondwires disconnect bondfingers.
0 G& k% \- Q* a! J5 F% c663088  Cannot add connect to a C-line in Etch Edit Mode
663220  IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in
' P$ j& p# \; ODEHDL
2 ^& n" d/ |7 b% N2 e( _663726  ?Each? menu under RefDes is missing in BOM HDL user guide
8 d( r: @$ Z+ b  @* h8 n664764  Material changes when layer type is changed 664900  Project manager User Preferences Editor form has text crop.
665236  Unable to import a Quartus-II version 9.0 pin file.
4 S' [5 W4 E% d2 ~( W' D9 D6 I. v, f665389  Spread between voids not working for customer design
665413  In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
  Q  X7 i0 V- }4 G0 B+ s7 x665451  Import - Part logic - information popup window has incorrect user preferences Editor
% \/ F7 }" }: {0 k5 p+ JCategory
- P1 k% M" A& Z9 L8 p0 L665661  Wirebond Die Escape Generator failed to generate Clines
& p: G; L' j# |& ~+ \$ L2 K- {666099  Mandating at least one symbol with sizable pins for using size..1(not for size-1..0)
SPLBPD-310/SPLBPD-309 on reload
666667  Relational Table View Browsing Issue
7 W: z9 x7 X+ `  K2 ~667286  import IFF No Component Shape Line Via found in IFF file.
' R. p5 s0 S7 o' _6 j0 |/ {, g# c667751  db(v(out)) and vdb(out) gives different results for FFT
668080  Improve handling of curved routes
$ `. q, H; C" d' ~. a, \3 R  k8 r7 K668081  Capture Crash during Edit options
668393  Dielectric constant or loss tangent values do not update when changing conductor
668785  Capture not displaying variant values for Uppercase Display props
2 b. i' [# [% a3 h* h) `7 q" @* g668799  Placing specific part crashes OrCAD Capture
668876  Text on the Add button is crop on the Edit via list form.
# f: O3 P- V+ B4 L, v$ x668892  Incorrect Parallel Length data in parallelism report
* ~/ Y3 ]; I! @; _  u2 ]/ O669206  Parallelism rule causing significant performance issues during DRC update
; |. t6 T6 [  a  Q& A  w# k4 Q669238  Unable to use permanent highlighting for groups in version 16.x
$ Q; P8 [: }  _3 x$ o, y669323  Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated
& U' Q7 V% s  `2 {- @: U0 c- C669336  Error in documentation of DE HDL Reference Guide
: G4 h+ z# m  a9 @; H/ E! `670874  getVersion() function not reporting tool version
& H% B; I! h# _% t2 l: M- r1 i671811  Allegro extracta fails with more than 10 output files
672420  User defined property added to component instance is a function property in Allegro
672614  translator converts the symbol "\"  in the original Spice model to "[url=]\\\\[/url]"
672615  Translator generates 6 external nodes should only have up to 5 nodes
672618  Translator generates statement in the dml file: Language=hspice causing Spectre run
, s+ z. A+ j3 Z: e4 d4 g. qerrors
9 `( }& L3 r) d& l672715  Steam_out takes a long time and then fails but the .log file reports a successful export
673279  Same characters are listed as both valid and invalid in naming rules.
% @) g9 I9 M, O( C: e' R7 |; S673410  search by net name is finding electrical
" U( I7 \; t9 W: L9 l7 i3 i( J% h6 ^674058  Incorrect Variant Report
674291  Library Explorer fails to start and I receive a 'Runtime Error!' pop-up
674555  If the DSN filename contains spaces, autobackup will not write any DBK files to
675192  Adding a second BGA caused dsa_api.c to crash
9 H5 w1 H% \* s8 Y& c+ }675231  SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess.
6 M1 U* j; I) t) R: ?# P675562  axlWindowFit() documentation needs to be changed.
5 ~! s3 {  c9 N# p8 A9 \5 J6 ~675783  SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to
  K8 K# v8 w& O* e" S6 B: t- P: H8 Jbecome unplaced from alignment option
) g: c( Q- Z$ n( N( f8 j4 E676201  Cross section impedance not calculating with single license
7 S5 ]9 [- Y7 [5 j6 z& r& v- O% C676601  behavior of launch product from library manager
677582  mirror of die component on sip designs
( U, j6 P" G- z678013  Error: Symbol not found, though symbol is mapped in psmpath
678427  repeatedly placed symbols has strange instance name
678538  Why derive database does not transfer the Schematic Part property to CIS
678814  Spin a temp group will not rotate the symbol
678851  Difference in lengths in 16.01 and 16.2
678884  dbdoctor fixes corruption and then it's reintroduced
679224  dbdoctor states it fixes an error but the error returns
6 Q  u. t# i4 j, c. X. y" R6 V679960  Capture crashes from diff pair setup menu
% D( p8 ]( E: c: T4 z  U680565  Capture dsn files are not properly associated during install
681197  Report generator Hangs Up Allegro PCB Editor
682135  Justification of $PN placeholders not working in 16.2 release
682204  Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
682331  Incorrect reference to the middle mouse button.
683146  export variant path appears wrong in output folder while two DSN are open
simultaneously 683182  DRC0037 shows incorrect Alternate Net Alias.
  M' Q9 P0 P% t  U683379  ERROR in Measurement ConversionGain_XRange
684180  Sizable pins and vector pins cannot reside together in a component.
$ q/ ~* _; L- T/ E684661  via array created wrong results
684700  via array can not be placed on both sides of the cline
: R, T4 V0 \- U684912  16.2 documentation is incorrect for axlDeleteFillet
/ l$ t6 r9 N$ n( z9 x# A684915  Incorrect mention of creating graphics template in the PDV user guide
685685  When the customer tried to merge shapes, they disappeared and  do not merge.
8 I( y# w: c5 l686338  ERROR #8012 Database Operation Failed with MS SQL database
686560  Changing pin group property after pin swap resets pin numbers
9 @) ]1 b" ~" U3 V( R686736  Load property does not propagate to the associated MECH part
$ ?- X/ {+ a. d) Y3 a687008  ERROR 8020 after removing Place Icon
6 Z1 }5 E- u( G! M687074  Part disappears when you open it
687354  Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package
687385  Publish PDF outputs the net name (with underscore) overlaps with wire.
; ~" I6 K, z' Z) f687708  Smoke deration calculations for Capacitor
5 k4 f# |" V& R3 S  ^7 `& ~6 }' C687715  Getting Warning TJL will not be smoke checked
688606  Inconsistency in synchronization between bias display and icon
, C) s% J1 U* j0 j689542  Comma in ESpice model name causes simulation failure
690112  Ignored nets are displayed in simulated crosstalk worksheet in CM
691668  Stimulus editor hangs on doing change type
691740  crash when setting coincident uvias in CM beta testing 16.3
694139  Case difference of net and bus while generating FPGA netlist
: Z) B/ b3 q# n' X0 j694716  Waveforms are flat when using IO b-element in HSpice
( W2 S8 I% T2 t) e, _695109  Incorrect Diff-pair topology extracted by Paksi-E field solver
; v7 H+ U! S0 H8 b0 S6 `2 N695431  csv2ptf fails without providing any error message
$ k# M% z; c" r7 p, A) a3 w696273  Shape disappears when updated in CDNSIP 16.01 and not following the constraints
696534  Pin Visibility check box doesn't work while creating part from spreadsheet editor
# K6 A' }1 F+ I% z' t698494  Shape not getting filled correctly
- U* b- y4 @$ D/ F+ E1 y; P8 v700160  Error: TVCurve must start at time zero .
700644  Allegro Crashes on doing Zoom In
700725  Create Fanout with Via structure add structure from Top to Int. for bottom pins
701128  Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
: b4 Q( H; s# k5 G, {702557  Incorrect Behavior with FSP 2 FPGA Option License
( K6 h6 Q% z1 q1 g" g+ Z% B) K' C9 |703324  Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in
7 B* P$ O  N/ h: \& ~8 \704268  remove ARC and TOGGLE rmb options when in add rectangle or add circle command
2 N3 N: Z' `! h) N9 o5 m704317  Capture crash when deleting schematic folder
( K- u) p, M8 m0 p& ^5 |704475  Allegro SI change editor to Allegro PCB XL causes menu problems
705902  ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
705903  Cannot remove a matrix view after modifying the connections
, n0 C! y' M) K6 K3 Z$ t: U. o  @706169  IDF in error has spelling mistake
706613  Diff pair is not extracting properly through design link.
2 Q8 N% \1 x" o/ K+ d706729  Import properties fails with ERROR [IMP0020]
708134  Place > Manually command menus not refreshing the Placement list
/ T6 T4 u( I- k% i# b708145  Creating a netlist with Rev. 57AQ is not formatting correctly
( H& z# ^$ Z! D' S708634  Shapes getting incorrectly displayed in 16.2
710279  ERROR 8020# Place component operation failed.
710859  Unable to create Diff Pair from Autosetup
& T+ ]* M) U- o+ q. {( t3 J4 Z711739  selecting one component/symbol of class IC can move unrelated component due to
9 Q; Y$ @: H$ L4 W7 Iincorrect group membership.
712299  Internal application error while creating new design
712898  Netrev should not read PARENT_PPT_PART property value while importing the logic,
( I% d. M, s# r- o8 D; o' Ldue to which import logic fails
713465  Problems with dynamic shape creation over routed full-arcs diffpairs
713480  Display issue when adding a custom property to the first bit of the bus.
714072  Error while linking database part
714156  Capture crash while archiving project for external referenced design
716097  Specctra is crash during route.
  f+ }0 Z- E7 Q! r) Y716212  PACK_SHORT property gives package error for visible POWER pins 717484  Dynamic shape creating voids when moving a symbol
9 ~7 ]; T  i; j- A) y718151  Geometry not selected when we click tab for selection filter in pad designer
720092  Difference of behavior for slide for segments in options tab & RMB options
720191  Delay tune cannot keep the Gap if the diffpair segment is diagonal.
- a  H: ]9 U- R% j9 @# k720482  Include steps to Enable PSpice Menus in Design Entry HDL
# e4 O- R% @6 v- K" [8 I- X721415  Two buses are connected without a warning when moved on top of each other
721938  Cross-Section open error
722997  Hyperlink function does not work if zone info. includes hyphen
723146  Pb during compilation using predicate getFileStrings
723159  Typographical Error under "Synchronizing PTF Information" section
! n9 }1 ~+ Y: N8 k723235  client install results in incorrect, redundant, and problematic cds_lic_file variable
724414  State Wins Over Design does not reset the subdesign_suffix block values
724969  Allegro crashes when using place replicate function
5 {. U2 C6 R/ l  O& k" S' U' {9 P725852  Impedance has little difference - BEM2D
726731  SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in
" a% |% B0 s- h5 fbf not following snap
+ }, Q, r5 |& y726763  crash during logic import in Allegro CM enabled flow
1 l9 y7 m8 ], L: q1 K8 n9 n727663  Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly
729496  Build error in 16.3 and 16.4 cdnsip.exe

wzwang2000

呵呵，我都用16.5了，楼主动作有点慢哦。

jima

运行很慢，bug也多，不如用15.7的

suiwinder

有没有好的破解？

yjgyiysbcc

刚下载了
for linux版本
* Q" ?" y$ S6 S. Q& }& _1 _# w正在试用

T45524093

等待网友分享

cxt668

有那些bug呀

yejingang

BUG可真是多呀

elm99

Very Good

cassy

等破解完善了再下～

xiaocat85

有时间扔到网盘上给兄弟们

jobjin

Good

gleefly

一般人根本上不去,下不了