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Table of Contents
6 A1 g* C4 u/ g/ T( h, x- k( OAudience ............................................................................................. iii
0 T2 \7 d" d6 p) h+ [( TRelated Documents ............................................................................. iii
( A3 K+ k1 ?1 V3 KConventions ........................................................................................ iv
) k6 b7 t9 V1 L+ ^, c2 r" a3 S" K9 yObtaining Customer Support .............................................................. vi
6 D( a$ S4 S% Q0 ?; C X& c- {8 dOther Sources of Information ............................................................ vii$ x% P7 _0 {8 v2 F
Revision History ............................................................................... viii4 O4 S! y, i* k+ ^4 S. v3 n0 N% K
Chapter 1 - Overview of Models ..................................................................... 1-1
' M8 Y3 x/ |! ~% [% [# d( i" F( vUsing Models to Define Netlist Elements .............................................. 1-2/ Z3 {$ w, q; L: {% a( ^* I9 O
Supported Models for Specific Simulators ....................................... 1-2
. O1 z8 W3 g& u: N: W6 q& N' R& s2 D( BSelecting Models .............................................................................. 1-3
+ Y/ J/ O" K% V: [; f- U( z+ QExample ............................................................................................ 1-3
0 c0 B- _* n% |8 T+ B1 ZChapter 2 - Using Passive Device Models....................................................... 2-1# X1 I0 P% n' X3 S
Resistor Device Model and Equations .................................................... 2-25 O# \: M" F$ o) d! Y
Wire RC Model ................................................................................. 2-2
: u0 O! S. o; E% Q! t( tResistor Model Equations ................................................................. 2-55 K4 S0 m9 U. P' i5 q$ d
Capacitor Device Model and Equations ............................................... 2-10, q( Y2 S' m0 a0 W$ J1 h+ Z& Q
Capacitance Model ......................................................................... 2-10 [$ l# h' L: O, e3 M* n+ K2 L
Capacitor Device Equations ........................................................... 2-114 L5 R Q! Q6 k( k, {
Inductor Device Model and Equations ................................................. 2-14
4 m" p. s' W+ U' h" E6 e, g! d% dInductor Core Models ..................................................................... 2-152 m: d1 X7 T! T4 Z: j2 G. [
Magnetic Core Element Outputs .................................................... 2-18
6 U8 F3 C F0 @ t$ X; c: q# yInductor Device Equations ............................................................. 2-19
2 g! }( Q3 I9 o* _Jiles-Atherton Ferromagnetic Core Model ..................................... 2-218 q* _5 M8 |' y& B, y
Power Sources ....................................................................................... 2-304 n$ z8 ^- q" R2 G
Independent Sources ....................................................................... 2-30
, R- k# s3 v% P* }Controlled Sources .......................................................................... 2-33
% p9 k) d2 \; x# }Chapter 3 - Using Diodes ................................................................................. 3-1
& I4 }! X( Q, l& U, ^3 z( |8 A+ d% BDiode Types ............................................................................................ 3-2
9 h( ] ~6 q7 _ ]7 k( Z+ W3 v* KUsing Diode Model Statements .............................................................. 3-3
) c, V: L6 x/ F& LSetting Control Options .................................................................... 3-3
8 ?% e# c% J1 N7 H) A5 _! |: r% f; ESpecifying Junction Diode Models ......................................................... 3-5
. B# d) J# L8 g# M% y' w6 s kUsing the Junction Model Statement ................................................ 3-6: i4 n/ J% i" ^& K% z, D3 X! \) u
Using Junction Model Parameters .................................................... 3-7& t5 X9 N1 T6 o& w/ I
Geometric Scaling for Diode Models ............................................. 3-138 r0 v7 ~- E% ^% P
Defining Diode Models ................................................................... 3-158 B9 g0 t, X$ B2 j/ B% n+ m* [
Determining Temperature Effects on Junction Diodes ................... 3-18
- ^( O5 f1 L4 t6 D A, a: ` YUsing Junction Diode Equations ........................................................... 3-21
, H p, R3 A4 ]# x+ b9 G# hUsing Junction DC Equations ......................................................... 3-22+ J) i& D) q; |5 R; V/ W; |! \
Using Diode Capacitance Equations ............................................... 3-25
% X% q, i. l8 J3 m" x% f; f, Q7 yUsing Noise Equations .................................................................... 3-27- {# d6 H* p: i5 n+ q# r
Temperature Compensation Equations ........................................... 3-286 v- C. `& h( g: a
Using the Junction Cap Model .............................................................. 3-32
7 e, j& N9 \( U( D% B) i4 LSetting Juncap Model Parameters ................................................... 3-334 P& B- n3 `" ?9 g% P9 t$ r
Theory ............................................................................................. 3-33
q [3 u5 x! x* iJUNCAP Model Equations ............................................................. 3-381 s) e3 |9 v- q8 ]% J( k/ j
Using the Fowler-Nordheim Diode ...................................................... 3-46
; J* k3 g0 m7 Z! gConverting National Semiconductor Models ........................................ 3-48
u" `* V) Q; W! d: @Chapter 4 - Using BJT Models ........................................................................ 4-1# y1 ^" e9 X& ~4 q8 N
Using BJT Models .................................................................................. 4-2
3 ]) t2 m/ i' m8 s4 sSelecting Models ............................................................................... 4-2
* S9 Z9 I- p( k/ nBJT Model Statement ............................................................................. 4-49 j% l% R; \2 N5 V# e6 }* {
Using BJT Basic Model Parameters ................................................. 4-5% N5 I9 O) a! l! m! [: L4 t
Handling BJT Model Temperature Effects ..................................... 4-15; H: P4 _: F3 L7 ~$ {
BJT Device Equivalent Circuits ............................................................ 4-21
' M3 @" B; g7 Z3 P4 h) R% uScaling ............................................................................................. 4-21. T1 q6 s& ?4 Y; T' v
Understanding the BJT Current Convention ................................... 4-21
% c7 O8 s9 k2 _, AUsing BJT Equivalent Circuits ....................................................... 4-22- A0 G/ z1 N0 O/ a+ [ X2 ~( X
BJT Model Equations (NPN and PNP) ................................................. 4-30) N. o6 [5 Q5 V1 S
Understanding Transistor Geometry in Substrate Diodes .............. 4-30
0 I- L. w! T dUsing DC Model Equations ............................................................ 4-32
/ G/ s! S. X1 C& S( [* E5 x3 b0 w" _Using Substrate Current Equations ................................................. 4-33( ]+ D( i, t1 L% x
Using Base Charge Equations ......................................................... 4-34. C9 _0 g6 r- ]3 f
Using Variable Base Resistance Equations .................................... 4-35, a; U% g1 Z3 k
Using BJT Capacitance Equations ........................................................ 4-365 o: A( Z5 g: C5 j% q; m+ K
Using Base-Emitter Capacitance Equations ................................... 4-36
Q0 f i3 M* N @ i7 W0 IDetermining Base Collector Capacitance ....................................... 4-38
5 p: e6 B6 t2 O# OUsing Substrate Capacitance ........................................................... 4-403 q$ Q8 L) t' g3 J
Defining BJT Noise Equations ............................................................. 4-42
% e! g* G+ c5 _9 m6 C4 s: ^BJT Temperature Compensation Equations ......................................... 4-44
r$ U5 n$ X* }7 B* x ?+ s `Using Energy Gap Temperature Equations .................................... 4-44( G, w/ y5 K1 N+ i$ [* E: v/ u
Saturation and Beta Temperature Equations, TLEV=0 or 2 ........... 4-44
) t3 a% u/ Q5 Q/ w8 p! oUsing Saturation and Temperature Equations, TLEV=1 ................ 4-46
4 L, q, m, M! ~' k; Z @, m$ xUsing Saturation Temperature Equations, TLEV=3 ....................... 4-47
' V' |/ k6 m/ T$ {+ `6 ]0 o2 }* ~Using Capacitance Temperature Equations .................................... 4-492 d3 K1 H+ \$ w6 h9 T' n+ w9 y
Parasitic Resistor Temperature Equations ...................................... 4-51
. v0 ~- b8 u: a8 O# EUsing BJT Level=2 Temperature Equations .................................. 4-527 V7 a. y) y8 c* H6 A0 O
BJT Quasi-Saturation Model ................................................................ 4-53
k2 H" J" ?6 U1 R" d; Q# j |Using Epitaxial Current Source Iepi ............................................... 4-55
9 G6 j: _) l' ^0 ?8 f7 x4 `7 dEpitaxial Charge Storage Elements Ci and Cx ............................... 4-55. u' {1 X( m# D6 z8 h
Converting National Semiconductor Models ........................................ 4-58
) F7 l+ M% N& E5 t: I2 \& A1 bVBIC Bipolar Transistor Model ........................................................... 4-60* I+ {" p# b, l
Understanding the History of VBIC ............................................... 4-60 h8 ]' H) B2 S
VBIC Parameters ............................................................................ 4-61
- d5 G5 s& ~( u- I7 Q; A( eNoise Analysis ................................................................................ 4-62: ^. O* k. V; j) Y; J4 [ Q; V
Level 6 Philips Bipolar Model (MEXTRAM Level 503) ..................... 4-71
5 x2 u# }: m' d5 ^+ cLevel 6 Element Syntax .................................................................. 4-71 L' \4 Z7 c/ \ x% G
Level 6 Model Parameters .............................................................. 4-72
, p! W8 F1 B/ C! Y" j2 t4 ~Level 6 Philips Bipolar Model (MEXTRAM Level 504) ..................... 4-78& l6 f* g; q- Z( g. W1 _" N, v, J
Notes ............................................................................................... 4-794 I7 A4 R9 a' O& P3 B! d5 D
Level 6 Model Parameters (504) ..................................................... 4-80
/ X1 i+ h* \) F" LLevel 8 HiCUM Model ......................................................................... 4-94+ D0 W, J4 N5 g1 D
What is the HiCUM Model? ........................................................... 4-94
1 X" r. e; i. RHiCUM Model Advantages ............................................................ 4-94/ V; r1 v' t' {& ?) P! W# u
Avant! HiCUM Model vs. Public HiCUM Model .......................... 4-96
4 C+ R) H% r' v; }Model Implementation .................................................................... 4-96
1 [2 E8 ~6 W- A# m' bInternal Transistors ......................................................................... 4-977 c* T( y4 A* O* \: z8 i
Level 9 VBIC99 Model ...................................................................... 4-110
- z7 T2 X- J$ sElement Syntax of BJT Level 9 .................................................... 4-110
& [/ D' b( y0 u1 iEffects of VBIC99 ........................................................................ 4-112# J7 W) G8 a$ U1 p, t* W9 Q/ u2 {
Model Implementation .................................................................. 4-112
; L. m) H: |5 D( }6 N$ r7 j, ~Example ........................................................................................ 4-119
; r/ B9 W" P9 H6 {VBIC99 Notes for HSPICE Users ................................................ 4-123# i/ u0 q, I; y! ~6 m
Level 10 Phillips MODELLA Bipolar Model .................................... 4-124
( R- d t6 J5 ]8 _# kModel Parameters ......................................................................... 4-124
R# J0 y( \& D4 C9 j& s) MEquivalent Circuits ........................................................................ 4-1293 x) s. j: x& B
DC Operating Point Output .......................................................... 4-1319 v8 s ^. x# I! u: b) A1 Q2 h
Model Equations ........................................................................... 4-1329 c6 K4 f; Z c! B
Temperature Dependence of the Parameters ................................ 4-142
) c6 v7 u* R/ p6 c {+ f: S8 PLevel 11 UCSD HBT Model .............................................................. 4-146; P/ k! n, H: x) e+ i6 J
Using the UCSD HBT Model ....................................................... 4-146
3 a( R+ _" Z# Z+ c; s# zDescription of Parameters ............................................................. 4-147
1 H* } i( L# T" q' P* C8 s/ v3 FModel Equations ........................................................................... 4-152 i, N3 a3 S+ E) S% a
Equivalent Circuit ......................................................................... 4-1634 _) K% o/ S$ i( q) P/ x2 s( ?2 C p
Example Avant! True-Hspice Model Statement ........................... 4-165
6 I; z8 U9 r9 L' @9 v2 EChapter 5 - Using JFET and MESFET Models............................................. 5-13 a% n6 L$ B' P4 s1 t5 k
Understanding JFETs .............................................................................. 5-2
1 B6 w/ H1 g( h( _) x b+ NSpecifying a Model ................................................................................. 5-37 P/ f& ?! ~1 b% [" E$ D0 J( Z) x
Understanding the Capacitor Model ....................................................... 5-5+ y; K+ B( s6 I, q" v5 M
Model Applications ........................................................................... 5-5
; ^: a. s8 V' R; p" g) A" lControl Options ................................................................................. 5-67 q2 @# S2 _5 C1 w. F- X
JFET and MESFET Equivalent Circuits ................................................. 5-7
, b( j$ t6 s- G/ z( R7 X( uScaling ............................................................................................... 5-7
, E4 U. G# E& G+ K! n# hUnderstanding JFET Current Convention ........................................ 5-7' w @! x# {7 o4 f! q) R
JFET Equivalent Circuits .................................................................. 5-8. G- _8 p+ j5 q5 K4 g# {2 l
JFET and MESFET Model Statements ................................................. 5-13
* t. Q* j6 f0 t! TJFET and MESFET Model Parameters ........................................... 5-133 t. L' \7 l5 T/ H
Gate Diode DC Parameters ............................................................. 5-15
* \8 J* w. k# s- hJFET and MESFET Capacitances ................................................... 5-25/ L" O' `/ X. G* H8 H5 a) J; ~) n
Capacitance Comparison (CAPOP=1 and CAPOP=2) ................... 5-29
4 D! v+ n& q$ ]) B0 r4 |JFET and MESFET DC Equations ................................................. 5-31+ n9 B4 L1 D1 g. |5 \
JFET and MESFET Noise Models ....................................................... 5-35
0 ?' }0 c4 h( t3 b8 K3 YNoise Parameters ........................................................................... 5-35
: W/ F. p% j7 h# B. d5 R+ B" }Noise Equations .............................................................................. 5-35! g2 g; L Z' P+ }( ~+ S! n# M
Noise Summary Printout Definitions .............................................. 5-36
* z2 y0 p0 X1 _9 a$ ^% Q1 B" jJFET and MESFET Temperature Equations ........................................ 5-37
- J! W: {0 |5 KTemperature Compensation Equations ........................................... 5-400 x; _/ A5 h6 I. t! Q/ K
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