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改进如下：6 ]' j, s, l. r( _$ a7 A
! | J4 @2 h- }! m+ W) A
HOTFIX VERSION: 015
1 A+ @, H6 c/ i) V========================================================================================================: V9 V, z9 {% `' \, s9 @
CCRID PRODUCT PRODUCTLEVEL2 TITLE4 y* j1 {4 P+ E1 h" P) y2 ^% w
========================================================================================================
: t; U, K" |% t/ t1 l9 `264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip
# X. ?$ I. K# a# _609206 APD OTHER parallel command fails to run on mcm files2 ^/ c3 C; w, I
646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time* [* t$ I- r8 B* W; x
650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames2 W3 x8 T% e4 i. N! [: U+ W9 ?
665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal
8 e1 ]5 {/ i ` }! B666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import
9 ^* E0 p5 b. N) i" U2 s+ g* f# y! u669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n
" v8 E5 Z V9 a8 R+ \, E- b. M; ]. _669769 PSPICE DEHDL Edit Model on page border causes crash
* v0 g, p1 S* [# y- _671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.
! g$ n8 Z( G! b- g$ L672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl7 v2 U/ e1 z/ }' M# H
672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke
# `. y8 q" x( m3 _3 f672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa4 l* q" ~6 d6 {( o$ p
676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets1 d. p" N' u* y$ n7 {4 T
677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets
' S; G/ m) n/ o) F+ k6 v. f677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode. F q: v @* W1 F# j$ y6 [
678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license
9 u0 W3 C' ]+ \0 X6 t678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM
5 b3 `1 R7 U& k6 \6 A( E* [4 A/ M678794 SCM PACKAGER Unable to package subdesign' F" q/ k6 V3 Q5 E6 R l
678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2; u, @& c4 v; z- ]8 ^7 a" Y
678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced
) n& d7 |+ M1 Y5 b- M$ @( U; l679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns- p3 g) I3 B# ?7 r, N9 W) a
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i2 ?* }( J$ V5 u4 v A
679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo
0 ~2 B$ D% t6 V3 v" H. N" g679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.
$ \' z, J. x. S/ ]( e679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st! x7 u0 d4 x( ]* j: r
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri$ ^4 ^* r% q( f+ I
681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase
8 e9 l" [' T& t; ?$ A9 W. b681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if
$ L% K* I& p. k7 }& j: }9 w9 j: {682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte6 p G6 m; k5 A- s, R# N; T
683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
0 Q- e4 \+ J" n# X' F3 x683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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