C@dence.SPB16.20.winnt.Hotfix.001和002所更新的内容

zlei

HOTFIX VERSION:  002
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CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
6 Z6 L( [% p; p  u9 F  [6 P========================================================================================================
1 H% Z* f; h( @9 O. d% Y511865     SPECCTRA         REGIONS              Diff pairs should adhere to constraint area
" p) }  o8 B' |564589     ALLEGRO_EDITOR   OTHER                The show measure command should show the actually measured po
7 n* p0 w6 O, D% o4 e- h  G570861     CONCEPT_HDL      CORE                 Unconnected mark does not be removed even after wire is conne
572188     APD              PAKSI_E              3-D model extract failed
5 e8 @, Q" b" s7 s9 J& p; N578164     CONCEPT_HDL      SKILL                Cnskill crash during Create Test Schematic step when large pi
- F7 I$ T/ Y0 ]( `; Z9 s578874     SIP_LAYOUT       DIE_STACK_EDITOR     Stackup editor in SiP fails to add layers above and below top
580315     APD              ETCH_BACK            Etchback trace fails with error "W- An etch-back trace cannot
! Q' z' N2 H' Y& a/ V$ Y+ K582308     ALLEGRO_EDITOR   OTHER                Create Detail for bondpads rotated at (0,90,180 and 270) angl
594370     SIG_INTEGRITY    OTHER                Wrong description in case update form when changing preferenc
595755     CONCEPT_HDL      CORE                 Rumtime error happen when do Move Group in conceptHDL
597922     SIG_INTEGRITY    TRANSLATOR           spc2spc doesn not handle inline RLGC DATAPOINTS
606620     ASSURA           DRC                  Problem with density checks in Assura
+ D9 K3 l4 r# d$ Q, A  I609866     SCM              SCHGEN               Schgen replaces CTAP with COMMENT symbol which causes net sho
611678     ALLEGRO_EDITOR   GRAPHICS             During Place > Manual Pins disapear if component is on bottom
6 u+ c( m) r! t6 _7 z615630     ALLEGRO_EDITOR   GRAPHICS             Pins are not visible when place manually is used for Bottom s
: u; _- S# F8 c615764     CONSTRAINT_MGR   TDD                  BOM report does not filter parts with BOM_IGNORE
616529     CONCEPT_HDL      CORE                 15.7 Design Entry HDL fails with Out of Memory message
! B4 h8 {- P* M) n8 u( {: E( l: B616928     CONCEPT_HDL      CONSTRAINT_MGR       Net_physical_type and net_spacing _type constraints not sync'
# u& O& z6 |/ o( U5 o- L9 q& r617441     SIG_INTEGRITY    FIELD_SOLVERS        Reflection simulation fails when using wideband vias
617679     ALLEGRO_EDITOR   COLOR                The color palette will not be saved with the design unless co
617805     CIS              PART_MANAGER         Capture_crash
, ?' Q0 e# K. T  V5 ~618988     ALLEGRO_EDITOR   SCHEM_FTB            Long bus names being truncated
- F6 `  `' j7 u2 \( G& W1 X' k619588     APD              EDIT_ETCH            Poor routing performance. 5 second delay after each mouse cli
619691     SIG_INTEGRITY    FIELD_SOLVERS        Problem of EMS2D by using FreqDepFile
619867     ALLEGRO_EDITOR   DFA                  DFA_BOUND_TOP shape doesn't display DFA Audit conflicts
620359     CONSTRAINT_MGR   CONCEPT_HDL          ECSet and Netclass definitions lost in the FTB process
620424     CONCEPT_HDL      CONSTRAINT_MGR       CM restore from definition of subblock removes ECSets defined
620700     ALLEGRO_EDITOR   PAD_EDITOR           Shape has bigger void on Y direction for Oblong SMD Pads
; t! p4 A) o+ c620868     SIG_INTEGRITY    PAKSI_E              Wirebond material conductivity is not used by PakSI, only a d
620895     ALLEGRO_EDITOR   DRC_CONSTR           About error message of cns_design command.
620924     CONCEPT_HDL      OTHER                PDF Publisher 16.1/16.2 can not output some Japanese characte
" @, A( X9 E# R4 i' P621156     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
621163     SIP_LAYOUT       ASSY_RULE_CHECK      Ambiguity about the how is the 搒tart of the wire" defined in
& T8 ^1 Q$ t  I5 d* n( v# }9 m# T621298     CONSTRAINT_MGR   UI_FORMS             PCB SI crashes when importing a constraint file into Constrai
621315     ALLEGRO_EDITOR   PLACEMENT            Getting wrong component when using Place replicate unmatched
9 B/ U  X" S  t8 N4 Q621848     CONSTRAINT_MGR   TECHFILE             techfile write fails with Failed writing object attributes
621867     ALLEGRO_EDITOR   TESTPREP             Transcript window randomly locks up when running TestPrep
, H. p- ^! m; ?9 p+ g! [621901     SIG_INTEGRITY    OTHER                Incorrect extracted via drill/pad diameters and missing inter
622010     ALLEGRO_EDITOR   DATABASE             Undesired openings in Negative shape
622062     CONSTRAINT_MGR   DATABASE             Importing dcf file at system level crashing the Allegro PCB e
622156     ALLEGRO_EDITOR   SHAPE                Thermal/Anti value producing incorrect void sizes
622450     SIG_INTEGRITY    SIMULATION           Field solution failed
622466     ALLEGRO_EDITOR   COLOR                layer priority in 16.2
622566     ALLEGRO_EDITOR   SCHEM_FTB            Replacing the components of same refdes on board after import
' c0 `/ K3 b% T) u3 f" h* o  k622700     APD              PLATING_BAR          Plating Bar Check is highlighting Nets that appear to be conn
622862     ALLEGRO_EDITOR   ARTWORK              Allegro crashes when we enter a value in the field file size
: P* L# q/ @8 f622989     SIP_LAYOUT       IMPORT_DATA          Type of Wirebond die changed after die import
623182     SIG_INTEGRITY    FIELD_SOLVERS        Extract topology crashed
" J0 r5 O$ w6 q623300     SIP_LAYOUT       3D_VIEWER            Wrong placement of Solder Mask Bottom in 3D view file
5 w9 g2 q! p9 C3 _6 z" {623384     ALLEGRO_EDITOR   VALOR                Valor output showing padstacks on 45 degree angle wrong in 16
623489     ALLEGRO_EDITOR   EXTRACT              Allegro tools Report etch length by pin pair takes forever to
623529     ALLEGRO_EDITOR   EDIT_ETCH            Manual tandem diff pair routing has been lost in the 16.2 rel
623536     F2B              PACKAGERXL           packager fails with memory allocation error
5 z0 v  R8 |9 Z. Z( ]8 H$ e5 e$ J623673     CAPTURE          OTHER                Unable to get capture window size to full-screen in dual disp
623701     ALLEGRO_EDITOR   OTHER                'Analyze' menu missing when opening Allegro PCB Editor L - Pe
623738     CAPTURE          PART_EDITOR          Create part from spreadsheet is not working correctly
) N' z( J- q& J+ D/ P2 p623740     ALLEGRO_EDITOR   OTHER                Can we use variant.lst file as list file in find filter
623745     CAPTURE          OTHER                Capture crashes when the user tries to place markers
623813     SIP_LAYOUT       WIREBOND             Add wirerbond only is not working in this case with a bondfin
9 b% R. ~1 a& n% b+ B623830     ALLEGRO_EDITOR   MANUFACT             backdrilling is drilling through component pads on the bottom
6 q8 s) g, i& E" d# u$ I: N624048     ALLEGRO_EDITOR   OTHER                Viewlog for Export to 16.01 is not closing from any of the 'C
' k3 G5 u( D* [4 }- @: W624223     ALLEGRO_EDITOR   GRAPHICS             disable_datatips variable is busted
) D  G! G; ~0 z3 y1 g( g( v624495     ALLEGRO_EDITOR   SHAPE                Static shape did not void to drill holes
624599     SPECCTRA         ROUTE                PCB Router hangs on route of design
624653     APD              BGA_GENERATOR        BGA Generator fails at 400um pitch
% J4 P$ u# }# M3 Y" d$ r624812     CONSTRAINT_MGR   ANALYSIS             Importing dcf at the system level causes RPD constraints not
9 ^) m- z0 T- z  V6 v624888     ALLEGRO_EDITOR   DRC_CONSTR           Regions and RCI's Cset not working as expected
624958     ALLEGRO_EDITOR   EDIT_ETCH            Slide in region is changing etch to min line width
4 f3 @/ Y5 @1 t& ?  m. |625251     ALLEGRO_EDITOR   COLOR                16.2 Linux allegro - new subclass created does not reflect in
625273     APD              IMPORT_DATA          Import a .mcm into SIP in order to edit the die pins. Edit ->
625279     APD              DIE_EDITOR           die text in fails when the function name is >31 characters wi
625304     SIG_INTEGRITY    IRDROP               Need a better understanding of absolute current values report
' j- K4 Z) k9 ]4 u  \625367     ALLEGRO_EDITOR   DRC_CONSTR           drc_fillet_samenet does not work correctly
625551     ALLEGRO_EDITOR   SHAPE                Dynamic shape is not voiding to route keepout correctly
625852     ALLEGRO_EDITOR   DRC_CONSTR           Some buses in CM are disappeared after import CIS 3 .dat netl
& g4 U; i: \# |625885     CAPTURE          DRC                  Report misleading Tap connections check for DRC reports error
. a6 M% u* S% E4 S, O625972     CONSTRAINT_MGR   TECHFILE             techfile import fails with Failed writing object attributes
, T* J6 }5 v: k! ]; w  W626630     CAPTURE          NETLIST_ALLEGRO      Capture 16.20 hangs endlessly but Capture 16.0 prompts result
626669     SIP_LAYOUT       OTHER                16.2 radial router find filter does not have option for bond
: J) N1 K# p; }3 ^626671     SCM              OTHER                Adding signals in ASA is taking too long
627228     ALLEGRO_EDITOR   MANUFACT             Dynamic Fillet is disappered, when use slide command.
( ^6 J# U0 _6 X5 Y0 e) P; z627289     SIP_LAYOUT       DIE_GENERATOR        Pins connect at the same net name after Die Text In
5 j% L5 m# F/ t- d% Z627864     CONCEPT_HDL      EDIF300              EDIF c2esch crashes
  z$ h/ l, x/ y( \3 m, b) c628169     ALLEGRO_EDITOR   OTHER                write command changes design name in constraint manager
& g! n& p" G7 l: w1 e; Y7 E8 j628220     SIG_INTEGRITY    SIMULATION           Reflection simulation failed with filed solver "EMS2D"
1 a# J3 v: A5 {+ W628261     APD              OTHER                no "Tangent Via Line Fattening" in APD products
$ V8 W; K6 z) l628922     APD              REPORTS              Metal Area Report shows 0.00 on one layer
HOTFIX VERSION:  001
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/ D+ ?. f0 O% K" ^3 Y, WCCRID      PRODUCT          PRODUCTLEVEL2        TITLE
' L4 \5 C; L9 B$ H" D1 Q, C3 Z========================================================================================================
7 T* _3 D! g' D' I0 x: t191020     ALLEGRO_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
7 W; w" C  S6 _) K$ c% r& m0 Z230469     ALLEGRO_EDITOR   SHAPE                Allegro improve performance of Dynamic Shapes
8 w6 ~+ a7 H( @" o295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
0 `; B* c- z, Z) `346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
400036     CONCEPT_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
4 h) ~) ^6 X4 [) X9 u& w* w415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
+ j  R8 w2 U/ N% e2 a' O# N503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
& f* P0 ]% d* U. x- z5 E511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
4 Y1 y$ m8 U" X5 ]$ B( l526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
! `+ Y* o7 `' z! _5 {: y3 g& {533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
- D- t9 \& c9 `' E4 [# R" n537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
544519     ALLEGRO_EDITOR   MENTOR               mbs2lib Generating extra "b" version of footprint during tran
( l. P0 t! Q# `# @% i( d3 W551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
; J) K: [" S+ ^552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
& y+ i, m, R2 s4 ^. p: @$ E560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
% T; ~- C1 _; I4 R1 N! V9 s* l564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
% P1 J" H1 u# c! {3 z# ]565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
# V& D5 F, i  ~1 c571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
, m" D" @6 l! R, H! ]+ E4 X581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
7 @% V2 U0 ~4 @; B' D2 B586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
6 _. y9 @# N1 t/ x0 o: y592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
* X4 g( K1 V( h+ Z' U596530     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro Translator removing/renaming reference design
596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
596716     PSPICE           DEHDL                Flag error due to part pin mismatch while create netlist
597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
$ O  E4 \3 M5 m7 P: F- t7 W1 E" Y598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
: D( K  t* s5 P. z599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
* F3 d0 X4 i8 T- e2 F- Q604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
5 u0 ^) T9 F3 j604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
) Z7 Y3 B8 O1 F  B2 `604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
4 _& @( L" g; n  ^$ _/ [2 [607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
$ g/ Q+ e5 c, a! l& N& I: C: B607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
) i  m; _# @+ p! q  w609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
& G0 n; W3 I" q6 u4 v0 w& ~610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
5 g6 x& j6 }9 D" _610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
, k) U4 u; w: F2 w$ s611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
1 p" I' j' p# l% E611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
8 J8 L+ D5 M5 ?, G3 q611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
) B3 c: O* E1 D! k612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
612237     ALLEGRO_EDITOR   SKILL                axlFormColorize does not change the full background area of a
612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
2 |8 L! w0 s' X2 L8 L/ c1 _( [8 g9 H612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
$ ^: m$ |" F# _. W! C613736     SPIF             OTHER                Spif fails to write class data
613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
4 }0 m- t, r' _; _' Z614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
. n8 ~0 u% f* g7 q. p" U614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
" m; p( c( d1 j5 D2 T614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
! b3 S; }! c' q. l* u8 q  o8 ~615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
3 \9 L4 D# Y+ o/ G4 w615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
. V/ o0 I+ a0 Y- C# Z9 Y1 z- ^" Z615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
" p5 d) ~+ Z+ W( @616122     LAYOUT           TRANSLATORS          Protel to MAX translator problem with package outlines and re
616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
- B# W- I6 M; u5 P/ ]' y616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
7 y' P/ Z: N$ L4 |& W6 g616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
% |5 t+ o8 x. A& G6 `8 e617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
; X2 ^4 V! _9 D; B; `; m' ^& u- @617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
/ T4 L' C! U# V" K, s617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
" f3 x3 d; M7 k$ Y617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
/ {9 {- Z( [3 }6 A2 X7 N617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
) x( S  a7 u% F* Q617761     LAYOUT           TRANSLATORS          Value property for Library symbol of Orcad Layout is not tran
617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
618184     APD              OTHER                database diary on unix/linux
1 I: n9 w4 D6 G; T7 `618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
, f+ g  X+ s, q9 Q/ r$ q618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
- M$ @: v- p8 U! `1 p7 V( [$ @618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
' j! B8 ^: s2 ^$ ?- Q. z618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
619033     F2B              PACKAGERXL           Pinswap lost on backannotation
619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
9 |. g3 \- I2 g1 w: \619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
9 f8 O, R! M8 M8 B* i( A620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design