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Electrical(电气规则) 3 s8 W3 y% t7 _$ }) P; {: e ~& D
Clearance(安全间距规则) 3 M& l! w4 S/ g( l7 g; a4 x( s4 H
short-circuit(短路规则)
# b2 E0 W) i. h J1 I+ b2 }; a5 u Unrouted Net(未布线网络规则) $ C* s3 ?* w$ ]6 w4 Y
Unconnected Pin(未连线引脚规则)
" s1 d( h* q% X5 r/ @Routing(走线规则)
/ W% r, U F" I6 v4 t) J: S Width(走线宽度规则)
$ s" ^! z% m- ^+ S) h0 u Routing Topology(走线拓扑布局规则)
/ Q' M$ O d. ~ Routing Priority(布线优先级规则)
6 u) S6 a9 C% d0 }$ d) x1 y% t9 s. U Routing Layers(板层布线规则)
8 D" q# H5 x3 A6 N* f# A3 K Routing Corners(导线转角规则)
" e$ V, R+ D1 b: i0 s' D/ D Routing Via Style(布线过孔形式规则)
7 \6 Y% G, n+ } Fanout Control(布线扇出控制规则)
6 n4 g. s6 l x/ aSMT(表贴焊盘规则) 2 q! k( A/ V, b; r1 Q! F; {6 N
SMD To Corner(SMD焊盘与导线拐角处最小间距规则) ) Y n7 Y" O, D' C1 E
SMD To Plane(SMD焊盘与电源层过孔最小间距规则)
4 p- o& u2 F2 L! G! T( Z( \ SMD Neck-Down(SMD焊盘颈缩率规则) - C" I! u2 L: P4 g
Mask(阻焊层规则)
& e; B" J- }. q' p6 D Solder Mask Expansion(阻焊层收缩量规则) 0 N8 c$ j5 r8 D1 _
Paste Mask Expansion(助焊层收缩量规则) 1 ~" t; h+ i2 C B( E
Plane(电源层规则)
2 N( d8 j! N2 E+ q$ Y% ?; [& V Power Plane Connect(电源层连接类型规则) 1 S% f7 i' R0 y4 c& v# R3 W
Power Plane Clearance(电源层安全间距规则) 8 |+ i+ ?6 ^$ x, M6 Z. n. ]* i. c: P
Polygon Connect Style(焊盘与覆铜连接类型规则) & U# p- M3 G) H3 l1 \# H
Testpoint(测试点规则)
' v5 w: k2 B" u, B Testpoint Style(测试点样式规则) ! B7 ?9 c8 s& v+ H* H& _
Testpoint Usage(测试点使用规则)
& `" l5 Y0 e# c8 z/ T! }: pManufacturing(电路板制作规则)
d% N# ]4 r! `+ T0 J7 d Minimum Annular Ring(最小包环限制规则)
7 t4 ^& A- f0 Y' C$ g# V Acute Angle Constraint(锐角限制规则)
, O7 q! L2 o6 g( l i* V Hole Size(孔径大小设计规则)
; I! R% r% P! `+ _: x( g; l Layer Pairs(板层对设计规则)
0 D) C) V0 T: OHighspeed(高频电路规则) 6 K; O$ A0 A; S: l
Parallel Segment(平行铜膜线段间距限制规则)
' g) F4 N+ r i; x5 G Length(网络长度限制规则) 0 d7 b" }$ @- W+ x
Matched Net Lengths(网络长度匹配规则) : t' H" K" P" Y) y0 w
Daisy Chain Stub Length (菊花状布线分支长度限制规则)
1 M- a& t( M3 b* H; ~ Vias Under SMD(SMD焊盘下过孔限制规则) 3 ?" s; W ]' |; ]+ E
Maximum Via Count(最大过孔数目限制规则) & c# C7 e8 h6 i* f
Placement(元件布置规则)
+ D6 U7 u2 Q/ K+ m Room Definition(元件集合定义规则) . } u7 [4 @7 Z: |
Component Clearance(元件间距限制规则) ) n1 r' |% t" {* x$ B$ D5 A# G `4 L
Component Orientations(元件布置方向规则) " j- ^# L; N- I! N
Permitted Layers(允许元件布置板层规则)
$ ?# [5 `& F' T" ^ Nets To Ignore(网络忽略规则)
, l6 L. j6 m4 B$ {9 A5 t9 \( q Hight(高度规则) " {' `1 _# u4 x; M' p
Signal Integrity(信号完整性规则)
% x! i U i3 ^# H7 M' } Signal Stimulus(激励信号规则) 5 T; D1 j( @ ]( g
Overshoot-Failing Edge(负超调量限制规则) 7 M5 k: ^: M' j/ {+ `
Overshoot-Rising Edge(正超调量限制规则) 7 |2 ]& {+ O2 Q: D/ S9 z: P
Undershoot-Falling Edge(负下冲超调量限制规则)
. H1 }+ B: h0 Z/ ] Undershoot-Rising Edge(正下冲超调量限制规则)
# h$ f. Q* Y& W, b6 P Impedance(阻抗限制规则)
. T' R; j' {. L9 x6 X: W Signal Top Value(高电平信号规则)
6 \6 p5 J" g- J; g7 S Signal Base Value(低电平信号规则) * l8 t8 y; f% m
Flight Time-Rising Edge(上升飞行时间规则)
4 v1 S) D$ U0 e9 d: r8 }; h# y Flight Time-Falling Edge(下降飞行时间规则) \* s2 ?- F9 s, C
Slope-Rising Edge(上升沿时间规则) + q' z3 M y' {6 B/ Z8 [
Slope-Falling Edge(下降沿时间规则)
+ C2 t1 ?- O( H+ E Supply Nets(电源网络规则) $ l+ M$ Y. _7 O
" C0 F9 f( h3 i+ C
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