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Electrical(电气规则)
1 d% d& X% F; \0 s Clearance(安全间距规则) # M( c4 B7 D' m- b; `' r
short-circuit(短路规则)
7 y; Z: w* E) ?- W7 J Unrouted Net(未布线网络规则)
' m1 U8 j8 h) _) i- U2 o7 d2 q. z: `' Z) P Unconnected Pin(未连线引脚规则)
' {8 [* L" @; f% i5 l, `- I" dRouting(走线规则) $ G+ U' @' B7 s6 I! S% i5 s$ u5 A# V
Width(走线宽度规则) 8 c& l2 Z5 p9 ~. J; x! x7 B
Routing Topology(走线拓扑布局规则)
1 O, n8 d3 |: `2 U; h+ c9 V9 ^: ] Routing Priority(布线优先级规则)
; z7 A4 y5 ] h! y* J/ g Routing Layers(板层布线规则) 9 g# Q! U6 Y# Y' h/ f' c
Routing Corners(导线转角规则) % ?; I9 c8 ?8 u3 c7 Z/ _4 }
Routing Via Style(布线过孔形式规则) ; e; E. c, Q" n* `7 d; f; `
Fanout Control(布线扇出控制规则) 7 }: |/ r- `) \6 Q2 H! R2 X
SMT(表贴焊盘规则) 4 w0 F" G- B5 q- E7 ]
SMD To Corner(SMD焊盘与导线拐角处最小间距规则)
, \# ]7 h4 o( S. c( \( n SMD To Plane(SMD焊盘与电源层过孔最小间距规则) * J6 @& Q- a6 W. G0 d
SMD Neck-Down(SMD焊盘颈缩率规则)
) y1 ?, K3 k: Q# z ]' mMask(阻焊层规则) 8 w% T$ m0 @8 Y5 G0 U- k
Solder Mask Expansion(阻焊层收缩量规则)
4 T( T; Z' q6 y2 h3 L Paste Mask Expansion(助焊层收缩量规则)
2 v+ X! p8 E* |, h% dPlane(电源层规则)
) D# Q) l% U( r6 ~! j. D Power Plane Connect(电源层连接类型规则) 5 ?- @! H+ L) b) K
Power Plane Clearance(电源层安全间距规则) * n6 l! Q; c, s, A5 U3 ]6 F
Polygon Connect Style(焊盘与覆铜连接类型规则)
6 n+ S3 u: d# \6 q1 K' eTestpoint(测试点规则)
9 B# M0 q/ _8 T5 x; J6 m Testpoint Style(测试点样式规则) 2 m& n n1 N! y5 f2 a7 W
Testpoint Usage(测试点使用规则)
; E4 h5 N, m; U, D* H+ cManufacturing(电路板制作规则)
8 h; E3 b- g2 l Minimum Annular Ring(最小包环限制规则) 2 k* T. O' v, m
Acute Angle Constraint(锐角限制规则) & @( k G0 c& y$ t
Hole Size(孔径大小设计规则)
0 X2 Z% l* X+ L- l. y Layer Pairs(板层对设计规则)
" l2 E* |( I: I DHighspeed(高频电路规则)
4 A# m( X* ]# ~9 H3 J Parallel Segment(平行铜膜线段间距限制规则)
! E% ~1 d% [+ U" |5 [1 R' Z! V6 w4 g Length(网络长度限制规则)
* ^) R* L- c# I9 C Matched Net Lengths(网络长度匹配规则) / b9 r, Q) o$ w7 I* [
Daisy Chain Stub Length (菊花状布线分支长度限制规则) 7 Q3 ^$ u/ }' w# y' B' O ?! q
Vias Under SMD(SMD焊盘下过孔限制规则)
# N; T4 F9 f3 [+ q Maximum Via Count(最大过孔数目限制规则)
, i5 o! w. O) ~+ fPlacement(元件布置规则) ) @* V6 f* P7 \" a9 }0 X' A8 o
Room Definition(元件集合定义规则) 1 C, ]2 e) P0 ?9 c' o( d: Y+ A
Component Clearance(元件间距限制规则) * n( A/ V' O/ y) Z
Component Orientations(元件布置方向规则) . I5 M6 v6 K/ z2 G
Permitted Layers(允许元件布置板层规则)
! H; Y @4 h+ G/ P Nets To Ignore(网络忽略规则)
0 j" e& P; O/ r Hight(高度规则) 6 s4 W* m5 O& v2 e4 {* _# I
Signal Integrity(信号完整性规则) + y0 s9 J4 u% ?2 J, I7 _
Signal Stimulus(激励信号规则) 2 N8 }/ t2 b3 F
Overshoot-Failing Edge(负超调量限制规则) 0 i. P, X! P1 q9 o
Overshoot-Rising Edge(正超调量限制规则)
3 f$ |6 U- Q' e2 o8 [ Undershoot-Falling Edge(负下冲超调量限制规则)
# g" E E: W `! x7 O: J Undershoot-Rising Edge(正下冲超调量限制规则)
+ @' o- D4 D# b# V* R: `4 L. H Impedance(阻抗限制规则)
7 @' ?2 |+ d4 z) | ^7 f Signal Top Value(高电平信号规则)
) S2 S& M. t }3 H Signal Base Value(低电平信号规则) 2 ?* m0 Y/ K: J
Flight Time-Rising Edge(上升飞行时间规则) $ k+ M/ z. E" l+ y2 @$ ?7 \5 x( y4 ^1 Z
Flight Time-Falling Edge(下降飞行时间规则) ) u5 x4 ?: f# C, H0 [
Slope-Rising Edge(上升沿时间规则)
/ o/ {" H9 \/ L' ~' M2 ^8 Z Slope-Falling Edge(下降沿时间规则)
0 c* N4 v2 u8 @5 U Supply Nets(电源网络规则) 0 l) h+ i6 ^, Y3 v/ v/ v
7 K( {: }# j, h8 q* q( Q
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