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在网上寻找数字地与模拟地的英文材料;. d5 |- {, {4 c% q
无意间浏览到一个国外的的CPLD/FPGA论坛,点击进入
) g. t+ F3 m0 d0 E发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。! n- @' z- U8 a' }$ C: d) a6 }
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+ W- j* _+ ?" O0 o1 b8 M@: mc8051@oregano.at
8 F" Q/ Q. ~; I3 t- iW: http://oregano.at/ip/8051.htm0 A4 }0 p) D+ S
6 W6 B' p+ ]/ f3 m9 h f1 Q. N************************************************************
9 q2 h" P. h( ~+ C. W! ]4 v0 Z! LThis is version 1.4 of the MC8051 IP core.2 R% `$ J+ {# Q; Y
November 2004: Oregano Systems - Design & Consulting GesmbH
8 _; L$ E7 z5 Y* ?============================================================- k& F$ Q. \' x' f, g2 f7 @6 y
Changes:
( h* l$ {2 [% _. K) C2 G/ s5 C- corrected behaviour of RETI instruction handling
! O/ S* Q1 \ H+ `0 R. ?& k- added synchronization for interrupt signals+ R1 {* d& F7 @/ r- @" G) P1 t
- corrected timer problems
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************************************************************+ W; f+ Z9 k9 h3 F/ R/ [ x C5 Q
This is version 1.3 of the MC8051 IP core.0 y: g$ N* n4 R9 T! I" ?3 l
September 2002: Oregano Systems - Design & Consulting GesmbH2 y' j- E {4 _ }
============================================================: O; y& D, X9 E0 k
Change history:
4 z7 r% m q/ s# x/ J: H6 P/ |* T- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.4 k3 v" Z: L* h* \
- Corrected problem with duplex operation in file + M. k+ c! s, O4 q9 s+ x! w
mc8051_siu_rtl.vhd
8 [2 B! |3 m/ M1 v0 G. _
- {/ S3 @0 q" U3 f4 q1 h' ~# j3 D************************************************************$ u/ v0 q. |2 x- Z) T% c
This is version 1.2. of the MC8051 IP core.3 a" R3 U: @1 H% N) \
June 2002 - Oregano Systems - Design & Consulting GesmbH; R! {! N" f [9 u. R) q
============================================================, E3 ^$ U) _9 i
Change history:
( l( @; G. D, b% o7 M `- Eliminated the scr subdirectory form the distribution.
- Q( z, x9 R3 z1 [/ s4 i" `- Improved documentation.
+ b2 _! W8 | t8 T6 P5 \) L+ d' v( d4 j- Corrected several bugs in the source code (see the
/ J5 }0 q4 W3 q! A* O: W- R1 @3 K website for more details).
# H$ q- g! F8 k d( }/ Q- Improved the testbench with respect to the I/O port% g1 A8 C8 c" y1 G" s- T5 x- Q) g
behavior.
" a( s2 w! {5 H6 F9 \; o e- Enriched the msim directory with the assembler source w0 s1 }6 Y1 M8 Z/ q. H7 `
code of an example program.
% R3 p4 a2 Z1 b. C: f& L- Provided the source code of a Intel hex to binary( I% W" Z" o. o: {
textfile converter to ease simulation of the user's
; S" @, n& Q k) J3 V assambler programs.! w. \& ^, L( b7 k5 N; ^ r+ n3 \
' I! A/ X2 E3 f: B5 e8 ?4 u
************************************************************
( Z- [) p, c4 M1 f8 |+ f( cThis is version 1.1. of the MC8051 IP core.: b3 Y9 M4 [: F1 \
Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH
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下面是里面的部分VHDL. }) f3 B& D# O2 g, q. M
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library IEEE; ' |2 x4 B# r2 l/ S. T0 Y( ?
use IEEE.std_logic_1164.all;
2 a/ R+ Z4 e4 p/ F* x( _( Ouse IEEE.std_logic_arith.all;
' b# `0 j L9 W5 S0 v* ylibrary work;% c1 ~! c0 `. U
use work.mc8051_p.all;4 S2 J( }. f1 x9 h
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-----------------------------ENTITY DECLARATION--------------------------------
' D/ I9 H5 d) r" F3 ?entity addsub_core is
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generic (DWIDTH : integer := 16); -- Data width of the ALU8 C. O) t7 C2 \& R0 o
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);* I& r) e' W4 {9 O
opb_i : in std_logic_vector(DWIDTH-1 downto 0);: g$ w$ [7 v+ b7 \5 b% U4 M
addsub_i : in std_logic;
; [7 }% U1 P& s. I+ @( n, b: [ cy_i : in std_logic;
# J9 ?( o* G c4 j: N* } cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
# z: Z) P' J7 R; P9 P2 @ ov_o : out std_logic;' H2 e0 r' z) Z( P |
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
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# n+ [% H3 n' q0 t/ _. Hend addsub_core;
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entity mc8051_alu is
2 ~5 K! e {0 P( U# U# K Y generic (DWIDTH : integer := 8); -- Data width of the ALU3 D0 w$ E, D5 |7 {
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
* ^! ^9 Z1 i9 n! i" K3 \ ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);" r) m9 a9 v5 ]. h
acc_i : in std_logic_vector(DWIDTH-1 downto 0);
0 s* e1 o, V2 S- Y" c cmd_i : in std_logic_vector(5 downto 0);
" E8 r$ F# e& }" G5 K cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);; `* l5 Q& B$ w: {4 d. J
ov_i : in std_logic;: V4 Y1 W7 b" H& a" ]8 K
2 J1 ]: Q8 |' W( G; \. f new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);: i9 T. k$ {" _+ b; S7 p
new_ov_o : out std_logic;8 s. w! L0 O7 c9 j
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
+ N2 x. t! j' n5 @4 R$ l result_b_o : out std_logic_vector(DWIDTH-1 downto 0));
& s4 M, O* G8 V 5 F0 {6 u# G; Y( F- I* j2 [/ y
end mc8051_alu;; \$ X/ Q$ |3 Q' M% u- h
--Inputs:
5 x2 K# }6 o6 H+ t-- rom_data_i...... data input from ROM3 P' y# h' B9 ]/ W3 E+ L
-- ram_data_i...... data input from RAM! o* M. H2 \# g+ a* b( N I, z
-- acc_i........... the contents of the accumulator register
4 J( R2 V( q4 s, O. W$ o-- cmd_i........... command from the control unit
* {% n$ ?- S6 P4 H-- cy_i............ CY-Flags of the SFR
4 ?0 {5 [ U. ]$ R# L" m-- ov_i............ OV-Flag of the SFR
" h' f7 @3 }& W; B--Outputs:
1 |6 |# z% d# _% W1 u6 X/ Z-- new_cy_o........ new CY-Flags for SFR
6 K. J" N: G, `( w/ \+ K/ \" O-- new_ov_o........ new OV-Flag for SFR
- {& c4 C+ h! e8 Q0 }# v-- result_a_o...... result
8 O/ W$ v+ k/ I3 k" Y* `2 j-- result_b_o...... result. O4 X$ O L3 H! C+ [' X
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architecture struc of mc8051_alu is8 `% M& u+ |$ I7 h. f, d- {
signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);
/ f7 ~: e7 ^: _% O: w signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
7 E/ G) c8 Z* M, d* s* ~- _ signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);6 W) B) M- O; n( o; j6 }3 J. w+ A7 j; [
signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);' Q! H ]+ p. K4 `3 w; ]
signal s_alu_cmd : std_logic_vector(3 downto 0);
/ F7 C$ y- |6 D' v signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);
& I+ B9 F1 {4 o7 i+ s' w signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);
! j% h4 w) @# m1 j signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0);
1 z! T5 T" {) r5 T/ v2 a signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);+ d$ e0 y8 ]: s# [* B: f8 k# H6 Y% D5 z
signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);0 t; ^7 ~! o7 t( T! B
signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);, H7 J6 r+ C% g
signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0); \, p, _. c5 ]! a" Q3 X
signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);
5 X8 h) Q; ]: o: I2 }: j' j signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);
6 {" N$ e+ d8 f8 g' e signal s_dcml_cy : std_logic;2 q/ M6 K( m2 v# j) t
signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);
1 d3 r5 m3 j$ S5 o3 t signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);
1 w5 v8 E7 K& N% z7 I6 S0 |& d signal s_addsub_ov : std_logic;
. R0 `" j7 k$ K: r/ v. [/ B signal s_addsub_cy : std_logic;
% }+ J+ Z9 q! j) {+ I signal s_addsub : std_logic;3 d: b" \# B f" W4 p4 A
signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);
" L# H' h+ S2 @ signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);
# O1 F, o% _" a; w( Jbegin -- architecture structural
' H$ l M2 j: p; X i_alumux : alumux4 Y8 ]3 S" i, h( J0 h! Q# k0 [! S
generic map (- S) q; V/ D8 D- c. T/ u* F5 d
DWIDTH => DWIDTH)
4 V( n5 O. C" t0 ^: p |) _( Y: k# l port map (4 e3 b, m- R# G8 s
-- Primary I/Os of the ALU unit.* B" P H# Q% D
rom_data_i => rom_data_i, a. Y4 g/ u6 y* K+ i
ram_data_i => ram_data_i,
+ @7 {: d( B7 R; C3 X Y% I3 l acc_i => acc_i,
$ b# ?/ {1 S" W6 i2 ^* w cmd_i => cmd_i,
4 b& I/ z) A& X9 D cy_i => cy_i,
* D) r' u; o1 l7 q M ov_i => ov_i,
0 C( w8 Q6 R* t: p$ ~9 ? cy_o => new_cy_o,
`& O( e2 C9 v9 K1 u6 |2 r ov_o => new_ov_o,
" f0 p4 @: {" J* ~ @2 b4 _; @ result_a_o => result_a_o, Z, l& R. {5 Z9 ^- P9 u9 r
result_b_o => result_b_o,
, `( J/ g9 c% g$ i+ _ -- I/Os connecting the submodules.) r8 H- ~* W7 ~8 {! F/ r0 Q
result_i => s_alu_result,* \( S: J0 G) H
new_cy_i => s_alu_new_cy,$ q+ }2 N8 i+ E, I/ P
addsub_rslt_i => s_addsub_rslt,, l- ~/ Y- T- ]& C; Q& T
addsub_cy_i => s_addsub_newcy,
# ?' _0 x1 G# ? addsub_ov_i => s_addsub_ov,
! O( j* f3 }# a# U op_a_o => s_alu_op_a,
* h+ ?6 x* U N! h" n* \" { op_b_o => s_alu_op_b,
4 _( o5 F1 }2 V0 M( q) X) M0 Y alu_cmd_o => s_alu_cmd,
; C& d2 O- n R9 e W! y j# \ opa_o => s_addsub_opa,' ~3 t7 U6 o9 c/ v
opb_o => s_addsub_opb," [9 W1 m' Q2 C5 v* h7 G/ a: E
addsub_o => s_addsub,
& u# H) k/ r. o' } addsub_cy_o => s_addsub_cy,
/ e2 q# ]: Y3 |$ } dvdnd_o => s_dvdnd,4 b; P3 q. }* m5 f
dvsor_o => s_dvsor,
& L+ Y) J3 {1 W0 t# U4 O qutnt_i => s_qutnt,
& q7 K( C$ T9 d7 f: ]0 j+ y rmndr_i => s_rmndr,' J2 b; U2 ^( M
mltplcnd_o => s_mltplcnd,( ?+ G" d. E' R! b: s
mltplctr_o => s_mltplctr,
' w: I* D% V& u2 x% `3 S product_i => s_product, h) G+ ^, J5 w4 v
dcml_data_o => s_dcml_data,
2 {. j, G7 X. Q) z dcml_data_i => s_dcml_rslt,. i! O9 ?& t5 s/ e$ D5 l8 Q/ v
dcml_cy_i => s_dcml_cy);' S1 E* o: L* Y
i_alucore : alucore( N% c/ J f, G8 H# M
generic map (7 h) R6 a6 e( m* W$ g2 V% N6 k5 h8 {
DWIDTH => DWIDTH)
' i1 M$ D$ e% ] port map (4 h1 x+ w: j% s0 R# T" F
op_a_i => s_alu_op_a,+ ]: S# E9 P; w# ^
op_b_i => s_alu_op_b,( M: a5 u' A) i+ Z
alu_cmd_i => s_alu_cmd,
Q6 W; w; r' t. W e/ n cy_i => cy_i,
! J: ?2 `! |7 v. R w; p cy_o => s_alu_new_cy,
% S0 E6 A9 I, `5 r7 g g result_o => s_alu_result);7 K! m3 t9 g( Y
i_addsub_core : addsub_core
) h" q, o" `9 X3 C4 o2 Q6 n" S generic map (DWIDTH => DWIDTH)
7 x$ T0 \; Y9 ]3 \/ f) s h' ~ port map (opa_i => s_addsub_opa,
( F4 O+ Q* A/ g2 Q: l opb_i => s_addsub_opb,
U, x4 b% L( l$ `; f& s0 L* y- w addsub_i => s_addsub,
& ]) S1 U& H1 p* E" r; |5 L l cy_i => s_addsub_cy,7 B- K/ i1 @6 s" A
cy_o => s_addsub_newcy,' a# a! X4 ]1 _) l: D
ov_o => s_addsub_ov,
! B6 k% W' W( @' W: ^ rslt_o => s_addsub_rslt);+ A# L" T. T- Y) m' O- O: V' Y
gen_multiplier1 : if C_IMPL_MUL = 1 generate \+ B* U" D* }% w1 d: ~, d
i_comb_mltplr : comb_mltplr
& w9 G' s1 d2 }$ r generic map (
1 A9 x8 E! M- V5 @ DWIDTH => DWIDTH)
6 l: s/ C) t6 i8 ~3 {' _ port map ( _7 f; a: }1 x2 H0 _1 t' S
mltplcnd_i => s_mltplcnd,
! u; a ?& M/ Y$ l$ k5 I6 t9 H6 e mltplctr_i => s_mltplctr,
5 }5 y% ^. ?! S0 V* P product_o => s_product);2 T# ~- W$ O1 D s' p: e
end generate gen_multiplier1; W6 K+ n4 r6 i: ~# _# f
gen_multiplier0 : if C_IMPL_MUL /= 1 generate6 W1 Q; z! g3 I2 W8 a' l, t
s_product <= (others => '0');% K4 a' y l1 F( P0 C$ n
end generate gen_multiplier0;/ C0 o' ?4 \) Q* U# A( w5 z" C& {0 T
gen_divider1 : if C_IMPL_DIV = 1 generate
, `; C4 K. I7 R5 o) A i_comb_divider : comb_divider- G0 j; G& a$ M: {: D* G% Z5 e
generic map (4 S0 t& Z& z0 G, w3 ?' {
DWIDTH => DWIDTH)& \7 r8 J5 d; d! d$ _, \5 ^9 m8 ]6 F
port map (+ k7 D- D) k( V, P% w3 H0 p- w
dvdnd_i => s_dvdnd,3 F8 k! C, U8 b( p# j# @" [
dvsor_i => s_dvsor,, F) R9 m) G. j p( Y9 a$ h2 | g& E$ b
qutnt_o => s_qutnt,
% Q: H# ^( r, _/ n0 {% I rmndr_o => s_rmndr);
( v0 J1 Y! q+ T/ l4 | end generate gen_divider1;$ H3 E9 U0 q" g) A0 P) [- B
gen_divider0 : if C_IMPL_DIV /= 1 generate" @% i$ o1 G# I; T! Y& H
s_qutnt <= (others => '0');, L+ v1 M" ] y. q' x
s_rmndr <= (others => '0');0 \0 j+ w) o8 ?
end generate gen_divider0;' ~) f( [- ^- ~. I) E
gen_dcml_adj1 : if C_IMPL_DA = 1 generate
. ?: a) ?, W" D, e6 C5 f4 w i_dcml_adjust : dcml_adjust# P0 p( t, M5 @) r- @* {1 Z
generic map (
9 V. b! L0 O/ ]- ` DWIDTH => DWIDTH)
* m; \. {( Q" u# K port map ( C) j. A% B7 \( ^1 x B
data_i => s_dcml_data," G! g7 U( Q) W+ Y
cy_i => cy_i,
1 t9 V6 L8 E: `4 A: I* {& n data_o => s_dcml_rslt,
. d: u4 u* h# M: h cy_o => s_dcml_cy);: d/ P7 O" G7 \( c/ C
end generate gen_dcml_adj1;5 K' Z* s7 F- @
gen_dcml_adj0 : if C_IMPL_DA /= 1 generate
' x7 Z! N5 n4 j/ p: t8 a1 N3 L s_dcml_rslt <= (others => '0');
6 C- Q' P1 C4 v, x- @: W s_dcml_cy <= '0';7 w( s: u9 g9 T
end generate gen_dcml_adj0;& V; T( d$ c, x7 D
end struc; |
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