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本帖最后由 partime 于 2016-8-10 20:06 编辑
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不知道有没有人上传分享,我刚下载上传过来,现分享!8 i x4 N6 _2 k. e) q# u% U
链接在下面,回复可见。顶起来,让更多的人看到!还有CCR,可以看看都修复了什么内容。& ?# P$ P3 x6 t @
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CCR
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1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
; \, `8 o. a: b- i9 H 1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
! k5 f" U( n5 x! o( D* Q5 s* z& A 1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once0 x2 N! r) }* d
1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
7 x8 ]" x) K$ B @( h0 F 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found' Y/ |+ t4 _; \$ n+ @
1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes/ \- j! \) t, e; N
1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
4 C* V( u2 P: _3 P0 p 1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
7 I$ Y/ P& h( K- j& y 1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed
7 N3 G0 N/ f) O' Z, g 1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
2 s7 Y& l, @) e" l 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component( I5 r" M; T D( ~4 I7 w
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior
& L. D$ z+ P X4 T. H, o1 r2 W8 J 1590639 CONCEPT_HDL OTHER DEHDL crash when importing design1 f; R0 x% C& `$ N8 I* x) t
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM' l1 I4 U+ Q+ h. i5 z% L2 G
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified/ r( M$ e/ k' x; J
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view% X" l5 R$ z S4 w# j6 r( E, J! w
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
# H7 M! Y+ W/ U; V 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
, p3 p) n) w! I% U+ u, R2 C 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI$ O" `/ { X) j9 m7 z) m
1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas
- b3 ^" I/ g7 M0 ~# g 1598629 F2B PACKAGERXL Export Physical crashes
) i, V' p1 E( `) F- {' ? 1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
8 G" B* H- r# X7 t 1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
- U( K+ }0 P( u( b6 e 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
5 G& f3 p9 U2 }% _6 U: j4 i3 n 1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol& w! P3 [4 K8 O6 [ z c
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.. s6 ~- M5 k* r% f+ g
1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
; l4 v8 X: G ^+ [& v$ j3 v 1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project Z% M# W6 ~7 w8 c, x( F
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command( R1 S/ D' p% X3 u# V$ i6 k
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.& J& R2 s( v' D1 b" f! o- C
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
. U8 F7 c" e4 b) O: f9 e& ~& C 1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard
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