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DATE: 05-28-2016 HOTFIX VERSION: 071
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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, ]5 z1 d; T( `) T" V B1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets; B2 C" D2 X+ x3 }6 C- x2 o
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
* j; b9 _) r5 r; E/ _3 U# F5 K1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
+ B% w: v* [# D1 i7 l* r1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
3 n6 B2 ]0 t" ~# H1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.; I6 l( L0 A$ Y
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.$ Z/ c6 |; [1 _' l
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)* _) v2 l; L) i; ]
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
5 A: F7 c! e2 D/ @% A1 Y1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
D! [7 D$ t% D) c1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library. V. `' w/ |$ }5 U1 O* O
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG7 c1 u+ o) F/ a E
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon$ q' [" q0 Q: |% q
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets3 ~% n$ C. ?) K5 W* O1 s( k
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
9 X- m( u8 w9 ]% O& D1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
( P* w1 t% @! F& P1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
, }3 p7 p* o3 g2 N0 r7 C: D. h# X$ {1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins- w. D8 M+ @2 X: f! ~+ D9 R2 k) ?" G
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
9 f B" e0 W6 q% d" B8 x1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions7 [7 D+ @. M3 o% z0 a& c' t9 l8 M
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
) `9 D" }: _4 z3 y% r1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.1 W+ z* Y+ F7 w( V( t6 c' E
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
" b1 i" m& ~7 U @2 U/ m. z, _1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
/ T ~4 I+ k3 B9 r X- {4 S1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'! Z6 @% G& z6 W9 ]
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed3 m* t( N6 Z0 S+ j$ l+ Q' \. u
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
6 O5 B4 Y% T4 y2 Z3 g9 U1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager3 ]5 d+ G2 z1 P
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short8 [5 E% B( c5 {" R* z! u
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property F% @0 ]7 [1 W" m( k5 v. m. n: D
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only% Y4 ?) S: G8 n0 ~9 L+ [
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
. |( P. Y2 ?: s/ j. l1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)4 M4 a& G" _. a
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file9 [% X- l% d4 v% R
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
8 q6 @" ]2 k% l" [$ _1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'
% r; F9 E) r M7 J8 M& ]1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files0 f+ g: _% h# f3 Y* k9 O$ B+ a& V% k
. S; G" K, T- b9 w5 b
DATE: 04-22-2016 HOTFIX VERSION: 069
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
. O- w: k( W2 e1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode* o& C0 ]3 e% o& _
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail. s4 J! j, t+ B% \! z% p
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
, R% K, y8 M( U! C. G" ?; u! Q0 t4 j1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
& \; _+ [7 F3 k/ f1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
4 C$ T+ i. v9 g' V- I1 k* D1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals' u A" v+ C" O0 T8 Y
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
7 G$ G- g n7 C; P3 S* w {6 n$ u1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
5 H% c: p3 v0 l; e7 b1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
- r6 H& K* G. s1 T- W1 s1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
" j! D9 X& z8 r$ o1 t( s" F1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork8 t9 j4 d3 Q) ?4 J1 j' x5 @) J% s1 {
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
) k6 P% f. I( B. W/ [2 d" {1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
: |/ }; W$ l% @# s0 F i1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines1 \6 d8 I! `7 w9 t) m0 }' y
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
3 D8 [) C7 t! m/ `8 Y6 b8 _/ }* T+ U1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
) Q( V$ Q, r) E* U& Z& }6 P' W1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups3 J8 B, i, d' |' ~
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
8 F0 Z- K/ h n+ N h1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes7 u ?! b1 ]# j- v% f0 _
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
* ^& \: W. \ S" N, Q6 q( n5 o1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
1 r. ]1 R* i- Z2 O& t- O3 s1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM& u+ j. u$ e* J$ }9 d( J2 n
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error
6 w7 q# G( _/ I5 }6 r @2 r% |: V1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
5 l/ H) c5 r l' m6 w
& `4 H/ D2 a( U; q9 k: FDATE: 03-23-2016 HOTFIX VERSION: 068
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CCRID PRODUCT PRODUCTLEVEL2 TITLE! u: p9 ~+ C+ ] [. r
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% ?7 {/ A) T" _/ p! P2 {. k: A1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager" i3 h" k( I8 M
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
2 x2 ^% U, g" R& M1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
, d0 Z6 x. u0 v$ ` u1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
. b/ M/ ?9 r1 a" X5 {" Y3 D1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
% K9 ^6 n, o1 R2 s1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.1 w# E' U: K" u4 Q& d6 ] ^% F
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol' M2 j2 j/ T9 Z4 Z) O
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file5 n2 W) x$ v- F, k& [
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report: m7 I3 p3 q- t
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted') N! a) y/ [ D- Q! ~
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .. ] ^) }7 u8 n, k
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
' \( f$ u# A) @! ]/ @$ h- o1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
9 S0 T+ x% i* E N2 O; y" I( w3 J/ Z" ^
DATE: 03-11-2016 HOTFIX VERSION: 067# j$ D9 X+ ^8 s9 E" s$ p k9 S
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group0 ~' y- }! m8 B7 s3 |- |' T
1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines" \8 q3 S) i& P5 q! R
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error1 r5 b4 d- ]: {) ]
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
, f; Q: k0 R1 X4 @9 ^) g3 {1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
; B- q" t2 w- d) U: e+ f& [; y1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
. _! i% Y9 v% L6 g7 J& e* Q1 H1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
: k1 Q; C, K5 @ Y5 H2 E# l1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
8 k" t9 P( N+ T, ^7 y1 a+ U' O; ~, C$ l5 ]1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
- j; y9 I5 V0 o+ `( D% w1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager) u) E4 S0 b% I1 i
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters0 B/ _! \2 J$ c' `0 G8 u" T( D$ |
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
% `3 s _* p9 I$ p V% S3 i1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
& |/ d' N7 F3 H& {* K1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net4 V( O, f. a0 j0 D5 B
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform' S# N) m/ B. {& C* q; h
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.# _" i* f0 |6 i+ z2 D' x
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
: k7 x# T: P$ w& C6 l% U1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.% H: C. `5 c$ m' k: b/ a% W$ Z+ Y
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib" U+ }2 y8 n3 G/ u* G+ N1 B! q
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
8 G+ v/ d9 w. S S1 \1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
9 P, W$ l+ A$ K; ~8 E$ {: N1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board! {" `, d8 m! T) t0 c* M( ~/ _$ c
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
$ [0 k9 ]3 x& g& Q" r0 z1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
& B/ ^9 ^/ H$ U4 A1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
3 \6 S; ^8 M. f8 H1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
M6 N6 \' N5 A+ y2 k7 W1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with' Q H6 N5 F: [/ O1 I& e4 L
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
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DATE: 02-26-2016 HOTFIX VERSION: 0668 m2 \/ J6 ?# e1 t# @8 L5 _
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CCRID PRODUCT PRODUCTLEVEL2 TITLE* H, \' v- p/ H" H
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( [$ b" _; f) }. h. w6 d6 u. @1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
; N) S d2 `2 i6 x7 Q1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes* y. B. A; x, h- O
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
9 Y9 K1 K% b8 [, D& n* |1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message5 R8 B% @4 L4 q$ Q5 v" H. C
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
) i3 O. F- Z; W; ^ _5 ]5 Z1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue8 L% K3 p) o9 v( V {' u$ z3 K6 F3 [
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer- W* x8 u8 h% Q5 T
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins
* K/ i, Y: c" @: b8 k6 k' I$ V1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run& M! }% J3 N3 Q6 |9 a3 Q
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed2 g3 U. _( n) C: R( z: J, v: `
% E# M' ~2 x% IDATE: 02-12-2016 HOTFIX VERSION: 065
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$ u" ~0 R) i [2 S- e- P1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
% H' l/ c8 h2 q. t% [; F, m1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
- N( Z! Y+ j4 O6 O4 z1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
7 ^+ h3 Q* K" k6 q; b1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents." o( I) b& H; [1 @. L, @3 i, A
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms" U3 a" F1 |6 R6 w$ n r5 j
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
4 p. f( I! N8 F# ~0 l. {1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger
3 j& w9 ^1 Z8 f# L; D0 d$ t: `1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
2 B. K5 W& l1 y1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup! Q, _3 h8 ]4 Y! }; `: l6 s* |3 z9 {
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.1 q( L3 F$ e. A2 I
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DATE: 01-29-2016 HOTFIX VERSION: 064
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+ ?- h2 I" F& H$ h1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain, L/ {( |/ n9 [. v( s( V
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF5 i* N0 ~4 o! Q% a* ^5 i
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
5 |6 W3 a2 |9 G- {0 s1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected0 {5 V$ |) j+ y. c$ V/ u
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
0 q! x1 b3 a7 H, q* e2 q1 @; t( ?, {1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
& R5 a& R( q# f0 b: ?* w3 L/ P2 w1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas: l, C. F! X# u; T& }
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
' s6 Z( o. Y$ }2 y2 ~) W1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist } X; T6 X5 g4 @
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
1 m4 S: b, I( V# ~ J1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor3 ?6 n; ^ u J
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)( t/ n! b( H/ h2 h* O6 g4 V' s
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
6 v3 ]) X) w! J) l9 a. v1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash( C2 L9 f+ b: m5 D5 F. l+ J; ~
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
0 i. X5 L+ }1 ]5 Y: y1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
2 B7 g3 m) h; f5 {5 s1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
7 R0 Z: {/ e% h4 |! A! j1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
7 R% V9 G2 ~, W6 q" \& \" X1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes! I/ |6 @/ H' K! \- k
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DATE: 01-15-2016 HOTFIX VERSION: 063 q& B1 f H3 _0 \4 p7 ?/ @1 s
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
* |& U$ `3 E, e* U+ M2 A3 k- q( B" u1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
, y; t: x# i2 A: {4 j1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
; k5 y5 b6 ?, D4 p1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant/ |7 _, F% E/ g
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork, m( r7 y$ A p# d: N- E
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
6 N. a" i" Q: i5 M1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance. W! c% D) k7 v! `6 j2 \0 s& Q
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
. m: D. @ [& T3 _6 d/ N' p) G1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.. N( G; d- `% T
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out+ G: z& h0 I/ `+ v3 o/ M8 V9 e
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
; M6 {3 B) i9 d1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property
+ ~% C9 o0 b! U$ A/ D. ~0 _1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
: S0 ?7 l0 p' }$ w! d3 G( _+ {% O. Y1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
$ e& M: u( y1 G1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
( J2 k$ u& [+ Z1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'
+ V& N( V6 A" G+ [ `1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
$ w z: |4 H+ a# T1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
1 |' B* A0 E4 ~6 k1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas: O6 d: ~' [& o+ j
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports( z6 N, K3 w* D, z
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DATE: 12-11-2015 HOTFIX VERSION: 0620 r% L. W' q( C D$ h0 N
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* a- S% e& L+ L! U6 U' @0 k, v% q===================================================================================================================================; z/ c# L+ t" O$ x
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
$ y( {1 i& Q$ F1 W1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file5 h& q8 t# G$ x( w; u$ r
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option1 `, p) E" ^! e6 \% @! R7 l
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC. f4 _! X# E* y M2 B
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
' [% b4 y1 |' e! F* d1 ^1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked9 B, h- w% _. W0 e, R
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
% L; @' b5 B. G8 |8 \6 }& C1 x4 t1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
" w9 E8 T3 @0 I5 {) r+ A1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
; u' n @7 C Q) }* B1490311 SCM OTHER Block Packaging reports duplication when it should not, B" J1 P; G2 y
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'! [4 a/ U4 C t" t) k
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
' }' c. x0 J: q: G \4 o2 F- y1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)- V& `$ b7 U, \* j
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit1 X8 X$ R5 R2 T* v+ x
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout+ D- K6 j( q9 C4 p& ^: h
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
& C" O1 K; T- R1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types8 H, Q( h+ C8 x' V" p# V
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
' U9 D+ p$ ?% ~: M& l1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly5 K* ?# w; J1 _% e+ K
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
4 B$ B3 i! c( w# f$ J; k' m* }3 B7 b1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
% _* [9 R# W1 E7 @1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default- [: N6 M# }( Z
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
7 o0 ]) Z* q a* e# S2 f& p1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
* A. X F$ x# d ?1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out! p4 k: {, q: t" ?* ~/ ?% V
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF" x& \9 D. Q, ~2 I! @4 _& q
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form& W/ }9 ]8 x$ ~7 w4 N" B( T1 R
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
/ B! M8 w u2 G( d1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings' ]5 M; a& P! A$ X3 {
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
5 N# H& A5 _( R& q4 k) b1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized/ ]" }1 x# X- z) [
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
0 @1 F6 `6 N6 N- w" k1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
3 Z) @/ v% p8 s) H1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
: [0 ^. f, v% D( ~1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving/ f& [6 g- a m h
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None! ]1 _7 `& X7 E8 V$ x, i. h% n
- f- z* J0 P( v! o: F
DATE: 11-20-2015 HOTFIX VERSION: 061$ d$ P# y4 T+ {' f
===================================================================================================================================
% K. Q2 |( m3 p$ t% g9 B, d! ?CCRID PRODUCT PRODUCTLEVEL2 TITLE
) z* T( U* B' R* `+ S===================================================================================================================================
. Z7 i. t9 m( P. O1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
/ e% K2 [- p$ |- z4 f& _) S9 X1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init3 L ^: L. ^, f" \/ S8 ^1 x
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
8 S8 I* ?4 |" f5 t. }1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle' \2 `' Q% L: i/ s
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins2 f" v0 @4 a+ [$ I
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set$ y9 u: J& h# K. y) { t
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin" q0 ^" m) j; @# \( ?( W1 j
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools* x2 z+ ^: H& k+ I/ b
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename/ ^& c% C3 D9 _
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets8 i/ p T7 A, [4 i
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
# ?) w8 S8 L# r0 n1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy/ |' H k* t7 V
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
4 K% U( p8 j" P8 u8 B8 x7 @1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
8 y3 C+ e0 ^$ c3 t, w4 O6 M1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice. U5 r/ Y# r1 ~9 l- Z; q# z0 h3 \
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues/ M. |- i6 B2 f( S! V
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only8 n r; O5 Z# H0 l+ U- P+ s
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project" H4 O/ S+ h5 R& r1 E4 q' m
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
V N6 n: t, ~- i/ p4 S1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
) h0 N3 L- S0 {: v; t1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems; g: a3 ?% s L% T' f( Q
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported1 Y$ m" U" R) l `! ~5 J, S8 \0 e
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior# }) ~9 g7 g3 K5 O. f2 a
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
: P6 Q' A, I& z, J+ F& d& H/ z1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
& z& i4 v0 Z. U1490299 SCM OTHER ASA does not update revision properly( r7 ?) u R$ l( V& D! l
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
2 A, b6 h$ s9 R! [: G& ?1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
" A; J+ T V2 Y! ]1 c1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
# E! l# C+ u4 k, h6 K1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong3 r% Z( H5 V6 b$ z$ c3 ?/ L
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
4 d6 ~2 f( n" k8 u$ Z1 U! }9 `1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL) J1 Y* T$ J2 G
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC25814 F. A% ]) d' Y6 x
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size. b- F4 d+ h) D8 E
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root) Y9 R _% c& I* l) H- ?3 c/ A
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file+ t y( O. w; b/ z/ `8 r5 r
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05
