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DATE: 05-28-2016 HOTFIX VERSION: 071
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets* a; I3 m# K5 S \5 E
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package' c B3 C% |+ ?# ]. w
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser9 e N! u2 f; D" Z* Z
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
( ?# J h# P& N- u" Y1 q' q1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.- C9 w- T5 y0 }' H: j( f
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.6 E0 L1 N! X$ a
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
8 N; m9 g* A% D3 C2 B1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
% u- o7 ]6 }% J1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
. K( [ M g# k9 V3 g8 p$ r1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library& N" Z* g+ P( O/ ?' e; {
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG( {, n [. w/ J0 d2 _
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon3 a2 }2 b4 {: G5 ^/ {& O- f$ i5 u
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
# o' t+ m/ E6 f; s( M; f% o) ?1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open$ X' ~9 @' K: @8 a
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters" q U* j7 K/ W% M" P0 w
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC' `* _! b8 E5 G
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins5 y/ V7 l; i. b, l1 v0 y4 ~3 {
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas" f8 Q7 {; o0 G
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
1 F% h$ ~ L( ?" B: h2 G: E1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
, T; R! D- r* G! u1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.! _0 _% h4 A# P2 W5 F
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
+ n9 \% J8 |5 b( x ~1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
% r5 s6 }+ v% P$ i1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
5 |7 z/ K6 N$ ]5 Z9 Y1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed# d6 X1 \) E7 Q4 \
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
& M. [) c$ W5 z: Q+ p* z9 f1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
- x; z4 I: j0 S1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
/ H" ?( t& Y& Y) {; s1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property5 N, C" G- }$ G: l* Q
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
6 n. i+ u3 g/ m; U1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
1 `% d' P% Y( h; b2 K1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)6 f/ K( w, W$ N8 g P: h
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
! G W: J! i7 V5 W0 X( j1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
; {$ M5 I9 h: } \4 n X7 y" w1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'3 \: J' _' ^7 b/ g. k
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files% w4 z; S! N( L m* P1 I
# i9 b6 b7 R$ X v# | T; `1 JDATE: 04-22-2016 HOTFIX VERSION: 069
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: j2 s4 p0 E, q& \1 gCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output2 ?( R ~: W& Y
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode' h+ a' w2 q6 H4 A" |
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail+ D4 j# d0 `' {2 t) M5 V/ {
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
. k) g! D( X/ y+ Q1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
- R- Q8 p/ J2 t2 t8 D7 ?+ Z1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
, ]7 }, t0 n! P0 A$ U; l8 V% O1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
6 r, P, W7 J% j8 W3 n* V1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
5 l6 A% G( Z6 q' L- C, v) B1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed) X2 S: F* P4 n; D0 T6 i
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
& m. ?: c! L+ `3 d1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work- L3 O5 N' t" @
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
# B3 }% @6 {$ P1 ?% M1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
+ a2 t" B& O' k1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
: I/ k, y& u% ]. }6 v4 j! N1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines: E# Z! T) H3 ~. S% M* T: h
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems4 x2 i3 n- F; J# J1 b
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
% O8 x" h) a+ Q- R: | w3 s, \6 c1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
5 e* {2 p/ u% q$ \9 q" {1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
' S8 H8 [* y; f& T! {1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
8 G# `8 z- g" l, F+ n* s; z: c1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted6 a! J3 h, t$ n# j+ H5 D
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
/ p% c, M2 P `: s- E# C6 o, ]1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM3 j% k1 ]6 O; |5 z) X3 ^) S0 c
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error3 N% |7 n/ ~+ N. y! V7 P
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.2 X$ B! T+ ?. r3 R
/ P7 j* ^9 N' C8 q5 c8 U
DATE: 03-23-2016 HOTFIX VERSION: 068
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager1 N* ?( |& O' {/ _& j* R
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file2 I8 d1 G- n6 i* R8 I
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
+ s) ~8 Y0 C# K6 c2 k& u" Z8 |- e1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
' f, N- q7 {( W% z- m+ @5 S8 y; _" B1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
" P5 v- h+ t. R3 @1 k6 Q1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.! ~" g; T) j1 G. M; v
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
) j7 g* G* j3 t2 D, c4 l5 g1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
) S% b$ o2 Z; r! i5 ^1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report5 J3 o1 L: u3 M
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
8 f( u& C! R2 f0 ^2 w) M4 F2 @5 [1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .
, D3 ^; k( ?7 l4 p& q1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
9 e7 c& q. R# O1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols& j5 x, u# o/ D9 T
9 r+ J% H# F+ U" N
DATE: 03-11-2016 HOTFIX VERSION: 067
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group$ i+ S P; R" e
1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines( N$ K1 Y; T/ v+ V7 a( X a
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
$ ~1 }+ Z! Z: @7 L1 H$ b, L) u1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'% r/ M* E% D; L3 @$ [9 J4 Y$ U# a8 q
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
& L- V' \: D, p9 h& A1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
7 K1 A8 u j8 _1 y2 u* ]0 \1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file, w! X; \0 [, W2 R! L$ x
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
1 g( a- o/ X$ x' r6 Q! d1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing
9 N" Q7 c9 I* f9 @4 i- `1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager
6 R" i5 c% X0 Q# x6 b/ v1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters
: K; t+ R$ H6 E8 A+ ~$ E1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties! {* n" k( k& H6 A: s& I$ l: B
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer
* i9 X8 v2 V1 V" t1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
: ~- \: J7 \/ V) P+ r1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
' k, K( x" }' v' {" X0 @3 k1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.; x, Q2 V$ G: x; ], O
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error e# P$ Q% }$ e( Z% b" v
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.; P; Z( k) R5 ]7 ]$ f
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
0 k- u [( s* E( W/ N# T1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines, h9 E4 D0 q" n. y6 U' s
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
" X# n# o/ M% m3 b! [1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board% |2 ^* o N( B; F8 Z5 `$ ~
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash5 T4 ?$ U, b( W, C+ l! O" t& Q
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
1 ^- Z8 Q4 r' B% }. r% C1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked0 E. p+ J* r) P( s S
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.8 z; s" l8 x; W, g) H
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
$ v2 i% E* Q" b' k/ Z1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
. M3 O# \. T* |7 X q8 |& ~# F8 m1 O3 n! K5 W. l0 [, B
DATE: 02-26-2016 HOTFIX VERSION: 066
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
$ c' Q& ~9 A% S h2 T" g: v# G: A1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
, P v; G6 f, e2 @' t& b1 O1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions' w0 J, [2 z- P w2 H$ x
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
X! o8 r% A$ @6 E. ^, r1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr! ^1 ?5 }6 Q; Q4 M1 S
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue$ A; p( J7 N0 Q1 h- f0 V" E2 L
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer& b' U7 r0 n4 s& ^" k
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins3 C9 h1 z, e4 |" |, U7 w- g& K
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run4 p4 n, r* v6 q/ c
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed% V9 E5 B" C- Z, k
" e: T6 M; K ~1 o9 Y9 IDATE: 02-12-2016 HOTFIX VERSION: 065
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9 B( e& y: f: t TCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
0 z* `6 g7 |; r$ x3 x1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
: `6 y. m. X* _7 q1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit
8 Z2 W; [. L! M3 d |4 e) e1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents. \: p- Z1 h; x9 g8 j* d
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms/ F& z8 r7 w" s- Z
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine0 Z! n z. R2 a0 d
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger1 D' x+ ?% a1 ?" q
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design+ ?3 ?( z' D- I# O5 y
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup# k; H+ N/ c6 x/ N$ J: O" B( w/ H
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
0 W6 M& g/ f5 ]' }) R& k2 i! `5 f. m7 w/ _4 }
DATE: 01-29-2016 HOTFIX VERSION: 064
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- E. i9 }% t E" H$ C% m! Z9 {1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
' d1 `" L9 Y0 O) s. n7 {1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF8 D1 `5 k8 x* L( c- k, ]( X
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.
2 T/ ~: X$ d8 S* ], Z9 f1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected3 ^1 q7 d# _3 ?1 ]) |
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
3 u$ Q, K" |4 [6 h! I, u3 J1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
* S) K+ p8 e% V8 Q T2 m" R7 o& d1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas( j/ F9 s5 t3 `) ~& Q. I2 U& z! m4 S
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net4 A- ^1 @# g8 ?; O( v9 @
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
2 Q D! t: G& t. i6 Y1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
! Q: {- G, Y0 K* W1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
2 N9 w- C" x* C a* C! p1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file); T4 k9 I9 B8 K9 U! {5 v+ d
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design+ H6 ]4 `* h( I
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash. w8 h# Y( ~* [
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes7 W9 V( K- j8 v4 e! g v4 `5 {
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor' m' {: K9 k2 _% Y+ |
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct. ^) u2 ~, w* `5 Q. b
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63! t; U0 e8 K- q+ S: S6 H0 i
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes' }$ `3 _3 v4 L
3 c L Y; K4 t/ yDATE: 01-15-2016 HOTFIX VERSION: 063+ L7 H% D( }) n9 ~
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( w% U8 y& ?" `/ i* Z1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
/ x, W6 v3 H; i) u- \1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
* x# u( W* _0 @1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
}, J/ i% A& a6 P2 |" `7 z+ j1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
/ w+ f5 t- `, M1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
+ o1 O' k& v- i# ]& \1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
2 e& }' q% Y; o1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
$ L, q$ @( p- K% l+ k) i4 \5 E2 \1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
/ U' q9 ?4 J3 `1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.
4 S( ^9 J3 D3 E! R2 U% {4 \& p1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out
, y' w" g- ~# z6 x3 R7 a1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor5 q- k$ r+ R$ k
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property1 w" t# d4 N1 d, p, _1 A! a4 ?
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly) K" S8 i4 a6 S6 P1 O2 i, K6 ~
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
* w( Y8 Z$ @% @/ X1 b" z1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol& M) B F. M7 f# N( O
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.', n/ X8 J9 n o5 D* U* D; L) @
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
7 e9 N" |6 I7 k6 P* H1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
) N" c _* j7 D1 m: [/ X" m1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas% C' H2 M x% n; t8 ?
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports' L- V, }4 x/ _
. F8 I4 F, o; t' X
DATE: 12-11-2015 HOTFIX VERSION: 062
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, \/ O4 Q4 O* B; ~! D1 K/ P/ Y1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output7 B9 v; }% Z9 \$ B
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
: O; c9 C) a( _1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
$ ^/ T1 z" I! F5 h# h1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC8 V) b: ~8 X/ [! ?' m7 o
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
& p% Z* i& g6 _8 p1 U1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
* Y B& p7 p# a4 v% F% L( l1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.4 ?1 K& c6 e) j: F4 H" n5 j
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
' i* A9 |4 c& }: @- P9 @/ e1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
1 o; Q- n* S# o1490311 SCM OTHER Block Packaging reports duplication when it should not |2 X# V# T- I; U
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'& o9 h) W+ O. p1 }% l; D) K
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
3 Z4 v6 v9 q' Y0 O8 z7 o7 q1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)2 O& @, b% p4 E, U7 @- u
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit+ [/ d. ]' n$ ^( |+ R$ y m
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
7 \# g4 {2 v c6 V# @4 {& L! R1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )8 M9 d+ w: ~8 g* i3 y" f( M
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types2 o+ ~1 }7 f) c- @
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'% e( k3 ~, U# S7 t' B/ M; l
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly0 o; n2 e5 C1 s9 J- R4 @2 k3 v
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this8 `: u8 [+ e6 i+ g; m
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch$ v F, B* ?. g2 J9 I2 Z: x
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default, K, A( t4 s2 ]
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts/ C: D7 x, }. q+ N+ [2 |
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
\9 G9 O: S" b! j5 |$ r1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out6 y4 |, N& G9 W# L
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
& \7 ?5 E2 K* d8 |/ o2 i1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
2 u, {( n0 \9 `% ^% S( y1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
2 ?: z( L0 D. P! ? U$ I6 Y1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
4 Y6 o, m% w8 J5 L8 C( |& M1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location- ?. Z x" ^+ n% R O% J4 j& u3 f
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized8 f8 g; l) s3 J
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary6 s+ ^, R8 c2 ]' u0 _5 d( B* E
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
5 F3 v% Y7 x8 F1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin I5 d& J8 c3 N# T; F! \
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving+ b; x0 U, J6 ^/ W9 E1 M
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None! y, l" F3 G2 N/ v5 j
8 P7 n! M6 J6 t9 m3 n. N& V
DATE: 11-20-2015 HOTFIX VERSION: 061, N6 B. r+ T3 u2 B% w
===================================================================================================================================
' ^ f* {' m( k; ?) X0 FCCRID PRODUCT PRODUCTLEVEL2 TITLE
* m3 y: s# D4 l7 J% Z% F===================================================================================================================================
$ y7 h3 ?% J; V$ x7 J1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
0 G4 g9 |2 W% ]1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init, E3 A6 n- j- V5 c
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
- c: S2 I$ l9 V) h9 t1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
( `: a e9 q% V+ s# r X, D1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
+ K* R' g! U* \0 |7 h) |; ?1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
3 B# l. e7 _- h. Q# s- o1 V ]1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin6 @' ]$ a2 g9 x& M7 L5 W
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools1 Y6 }7 d8 A9 h5 v
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename, [4 Q' T. B z: z# r2 J a& y) c
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets. u8 S5 y# e5 ]
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
6 o/ T# U, f& M. J4 G5 v4 R, u) W1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy4 t. U0 ]$ v! i& ^7 T
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable0 J; Q) j/ I' P$ P0 Y- t' W9 r2 [( P
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets$ y* ]4 x- u$ Z; L
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
. z+ W6 S5 z6 e2 a6 e* V! T1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
! z5 C, N% r% N( T8 f! t" M1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only Z& {; i, \& L) M+ A9 x
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project% F. e/ J" T- Q( W( `
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.: z% P( B" {1 W
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility9 F4 n/ ?! I0 M2 a8 i9 n; O
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems+ x5 g+ X1 _) u: O, Q, n: r; q1 F
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported* X7 g# ?* H8 I! F& ?0 `7 S+ K
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
7 H' z) v2 O" g4 S, E! P# M1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
: |; h' l; ^* S2 \1 _- l3 M1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
1 G7 `1 a) ^) N* W( K% r1490299 SCM OTHER ASA does not update revision properly! \' A% ~2 J0 f- z
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer1 L% P) y3 T5 n5 q! u/ G5 d
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
! ?4 j. g) Z* _. X6 u6 ]6 R1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working% M. l6 l0 ~; ]
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
$ j& G# m* I9 ]' X3 ?$ k; E0 Z1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash4 E6 I- s. S |% i; R% G
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
( y: g, l' F3 p# I5 ^/ s/ q1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
* v: O9 |8 }* j) |3 x; J1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
2 Z, a4 o% e C* T9 W' D5 ]4 z1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root0 {6 t1 ?! B9 U. ^' `( w6 v
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
( c5 B+ W( r* `2 ]1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-17 13:05
