数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

zhangsong123

通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
, @- C$ g" L" N! g( Iinput clk,rst_n;
, a; _8 ^! r$ L' i1 i; C5 z6 uoutput [7:0]led;
6 _0 d6 d/ E6 x: |$ \% ~output [5:0]led_seg;
output SOS_En_Sig;
3 }% V8 R8 u! d' y; T) s( S4 H: S9 Qparameter seg_num0=8'hc0,
          seg_num1=8'hf9,
! A- R+ n2 H  W" U+ [, j" w- |- u             seg_num2=8'ha4,
6 X& o$ e- ^! t. l+ o5 {; I' V             seg_num3=8'hb0,
2 S( h3 O9 g1 w8 m; t             seg_num4=8'h99,
+ I7 L4 P0 M" q9 X* B             seg_num5=8'h92,
- s. V, n1 V) U! E, }             seg_num6=8'h82,
: m" T- E5 b  x/ F             seg_num7=8'hf8,
             seg_num8=8'h80,
             seg_num9=8'h90;
/ c+ N8 w. Y, C" [, C& Aparameter seg_en0=6'b111110,
          seg_en1=6'b111101,
             seg_en2=6'b111011,
) M" e1 R  I: [: H. K/ v- p             seg_en3=6'b110111,
8 p3 k& g0 d4 E) ]             seg_en4=6'b101111,
             seg_en5=6'b011111;
reg [26:0]count;
, g) d) r& _$ N7 B) M' y) Treg [3:0] count1;
! g2 l1 K/ ^% V( zreg [3:0] count2;
9 L7 q4 K& u) X7 lreg [7:0] led_reg;
reg [5:0] led_seg_reg;
- T. V( C; }0 H" n- z; o& talways@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
+ z* ?9 A$ P" l* }else if(count==27'd49_999_999) count<=27'd0;
' |4 }9 j" C2 \0 pelse count<=count+1'b1;
( y: L1 ~1 M9 q6 E9 o$ \' lwire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
if(!rst_n)
8 N2 F+ z: D6 `% K; u. [begin
+ V* Q5 v, t* r' z  Ccount1<=4'd0;
count2<=4'd4;
7 i. R# i/ h) t& |% D" xend
3 [' p4 X4 y) J, T; Ielse if((count1==4'd0)&&(count2==4'd0))
; _* ?4 R; ]/ m5 d, ~begin
count1<=4'd0;
' V. l. b. K" u6 t  Pcount2<=4'd4;
end
9 d% c% p6 `2 ~6 jelse if(count1==4'd0)
$ ~# ^& V8 \6 S# Y  Wbegin
count2<= count2-1'b1;
7 Z# A6 R; Z( ?+ ?count1<=4'd9;
5 {+ L/ y0 N% r! z4 oend
else count1<=count1-1'b1;
8 Y9 _' W' X/ l  z; ~reg [26:0]count_1ms;//
always@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
) x0 B8 B4 e, j' Y* Velse if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
! n9 n) q" o) K9 u6 f( Z( Kwire clk_dis=(count_1ms==27'd49_999);//
+ r/ `+ M$ h4 O2 m//
reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
if(!rst_n)
begin
/ w* V0 S0 x/ c" _/ Kled_reg<=8'hff;
led_seg_reg<=6'b111111;
( Y* z# s; ^' r( k% rstate<=2'b00;
end
else if(state==2'b00)
' J+ k. R: _$ w$ Q2 _6 Ubegin
state<=2'b01;
led_seg_reg<=6'b111101;
case(count2)
- Q3 i: O& l2 p4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
: `. h/ w9 F7 E% y. [1 ?4'd2:led_reg<=seg_num2;
/ z- s# S! j' c; g4'd3: led_reg<=seg_num3;  
2 x& G; O* k9 B4'd4: led_reg<=seg_num4;  
# b! L, v7 l8 P% Q5 Z4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
9 P: T; E$ B/ ~: D. _8 L4'd7: led_reg<=seg_num7;  
8 b) n3 ]( L) i" f4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
7 U$ n( \( j) H* w" r$ rdefault: led_reg<=seg_num0;  
- \) [; C; f& r# Q6 s# zendcase
end
: x; ?. }$ U+ x: n, M$ z; D% lelse if(state==2'b01)
begin
' A# a) t' h' G1 w' o! ^- gstate<=2'b00;
led_seg_reg<=6'b111110;
; S4 ^: O) H' s: \2 @* ^' Wcase(count1)
4'd0:led_reg<=seg_num0;
; X9 S" V( i+ @4'd1:led_reg<=seg_num1;
, U% Q; v" K- j9 j4'd2:led_reg<=seg_num2;
4 }6 V9 L% f: s) l) w0 I# I4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
2 ?; T' p( Z4 \4'd5:led_reg<=seg_num5;
' Q% n' f  T5 D5 g$ J, H4'd6:led_reg<=seg_num6;
, V7 k) [5 [0 k) d$ Y0 M* {4'd7:led_reg<=seg_num7;
' L: t2 F0 p7 C/ q4'd8:led_reg<=seg_num8;
4'd9:led_reg<=seg_num9;
- j  F2 B2 Z; \/ z% J& l2 j1 ~( |default:led_reg<=seg_num0;
endcase
: P8 e) [- Z1 _+ E1 jend
reg isEn;
always@(posedge clk or negedge rst_n)
, f* \6 S  v6 \6 e5 N, c+ ]! t& vif(!rst_n)
8 T7 }3 w7 |9 g& S* Mbegin
isEn<=1'b0;
- ?* \+ O2 c/ [  rend
else
! r: B  D0 b* U2 I0 {2 R" a) H* Mbegin
& S2 y, |# x- P. \; E! HisEn<=1'b1;
end
assign led=led_reg;
assign led_seg=led_seg_reg;
1 u  s2 _$ f8 }  d8 n, ]4 G# `assign SOS_En_Sig=isEn;
endmodule