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DATE: 07-31-2015 HOTFIX VERSION: 054+ K1 t7 `- F; W: Q% b
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$ V: b7 ~6 G: C694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL! O& ?2 T% X* V o( R
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions5 z# d$ I! I w6 f
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List
( b/ O7 T8 q- A6 a% V4 U6 Q y1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate* w4 n, `5 f1 t/ o, S k& j+ o3 X
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees
' d! }0 a, V# M- w" C ^1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias( j9 Z9 ?" X5 K% e7 \
1412635 APD DATABASE APD crashes on saving design
# `8 K! @! U0 Q4 P1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices$ D. E) ~7 I9 N- {
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation
* @6 }) q' p$ z0 J1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.
5 b7 T$ }8 Z- v2 S" D# [- a" I1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50" X# n% I j0 c) T1 x. I
1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
, r8 @& n6 b1 f5 Q' r1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
' {$ U; M( m9 J4 N4 d. P1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated
9 j' e* n9 W3 B6 i) b* H! i" O' y) ~1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
1 E; o$ h5 t+ }1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification
8 z% S# p$ d" S# d! Z1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.# p! ~1 u' u) z' J" Y
1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets- ]% ~ b. u$ K! T' _: }
1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor9 V4 R. A1 V7 _8 V$ u7 D
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow3 e `4 u/ y. d; l( k( J8 m
1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed+ v8 Y |0 m) V9 k
1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board
4 w" U& p' M; p& q H1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks" z6 r8 ~& [! Y* Z0 z
1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports) o, U8 K6 o6 b6 u, w+ B- x! C& a
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC
' V1 n5 v1 q5 U6 r1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary2 P0 h- }$ e& J, e. ?) |* z
1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.0 ~ S0 l ]4 P, ~) A
1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1
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' i W+ ^4 ?$ ~8 g9 x; j/ Khttp://pan.baidu.com/s/1mg28zJM
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发表于 2015-8-3 11:54
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