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本帖最后由 partime 于 2016-8-10 20:06 编辑 ( O' n' Y& H% V( P+ F8 f. P6 ?
2 f; a+ m' p* a7 o8 z$ [不知道有没有人上传分享，我刚下载上传过来，现分享！/ `8 t! c, m. C/ k
链接在下面，回复可见。顶起来，让更多的人看到！还有CCR，可以看看都修复了什么内容。4 N, O4 x+ m. X3 p0 v5 ~
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+ D7 _9 ^5 S* W [CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 y1 q3 k7 P7 R! V, o ===================================================================================================================================$ Q) E/ W5 y: x. u6 |1 X1 e
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result ^6 _1 c$ [2 Z i
1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S0665 g& ?$ {1 v& ]) \
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once, }6 @9 ^; L. l
1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly/ d4 g8 v/ h. d" P* q
1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
# [( U8 o1 T. z* v$ [4 M* u* M+ l 1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
9 M4 I* M- U7 \/ `2 m 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update9 m* E' C9 R8 ?8 ]: b
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties, |/ C9 [) ~2 t( p% y; M; e/ `; f
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed: [) \- b& p/ T" k' e" h4 J& E
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"7 Q1 I0 B }) B! x; d
1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component
6 B3 e" y0 }+ j. _; z7 y 1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior! j6 _% _. a$ L9 O8 I
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design5 A( J% l5 V9 g h' w8 @: \
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
. I1 _! i" z8 b! I; L0 f 1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified0 b$ o: d) H# @- P6 g& i; N
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
, K9 T4 w8 r2 z6 m8 d" x+ p 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
" [8 {& i' `5 T7 f 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
7 R/ w3 Q: @; P3 x 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
0 c! W q) x+ g) H2 x; @1 ] 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas2 N4 i" `& T+ o1 f2 K
1598629 F2B PACKAGERXL Export Physical crashes; Y1 ]) Z) H' c6 f+ [4 ]8 x
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
" M0 `! ^' K a/ b. P$ N 1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.# [" O5 G1 h: F$ q5 B9 `
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group+ _# O* Z& E! Z% y8 T. W% U
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
4 L, Q M( ^4 {+ `) y2 G0 L 1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
% s& Z6 e5 R- q; U- z$ D7 V6 M2 R; [) ? 1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses( |+ ]7 \& Z/ |; E: n
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project: W1 w& c. c6 O* A5 [& P2 Y
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command
, \* E! @+ P1 k/ r) k: A9 J9 R3 { k 1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
* ^& {! @( Y6 e% n 1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error! J0 \ R+ w' t" X* C+ D7 b) i t
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard
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发表于 2016-8-10 20:04
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