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本帖最后由 partime 于 2016-8-10 20:06 编辑 3 D2 ^1 G6 f) V& y2 g2 k
4 Z! L$ t- [) w! L" c2 D不知道有没有人上传分享，我刚下载上传过来，现分享！
. e: ~+ Q/ R' k1 F2 @, a链接在下面，回复可见。顶起来，让更多的人看到！还有CCR，可以看看都修复了什么内容。
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
+ y3 Z0 a( {7 _0 G 1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
- ~" \% Y) t2 C$ G 1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
% t) F# Z/ [1 }6 H. ^' i2 y0 [ 1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly5 U' D. h! a: d/ q
1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
- ?+ y3 L0 b, L5 s3 h- m) ] 1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
0 X) p" ^/ ]" h. n8 a- @5 C 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
1 C. `0 E% u; y; S! A# w% w 1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties0 _0 B, J; G0 ?2 B
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed' S9 P) O( C$ ~2 ^$ c5 }* y
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
0 b9 K: U8 U. d( V. } 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component. F! h" S X p L2 j; d2 L
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior$ o. Q k4 T% o* O& M
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design1 [4 ]7 J8 z$ B1 {) C) s
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM+ E, }0 J" b1 j# S. P
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified/ f2 m) Q0 k1 }/ v# [
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
" Z- K, J# F5 e1 z! H D* W! j1 } 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save# b' j% }; J" z
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
' E( b6 X' P( T w 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
$ D5 W, v$ v* b8 d 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas
6 f1 P6 a2 e2 g1 C* b* ?; Y 1598629 F2B PACKAGERXL Export Physical crashes( A2 T! O R% j0 W m5 Z7 J- K
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.9 E. |/ m5 ^ Z% K) S$ u5 K3 P
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
0 E8 G: i# F, M F 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group3 j# {/ M8 N. Y- Q; k1 o3 @
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol0 J0 y( `* b) l$ K. X' ?: \: R
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
* T U% i* ?9 |# d% n! s4 r8 I 1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
7 F+ h b B; D- W 1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
0 W$ s+ D9 l3 p- ~( l- F 1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command
) a( ]5 J3 v( v4 |* J# s 1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.: C2 F/ g) [6 Q" O& w
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
, M9 S* x2 F+ o0 m, l 1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard% W$ @. o R0 W3 }# B9 e
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发表于 2016-8-10 20:04
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