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本帖最后由 dsws 于 2013-7-1 20:32 编辑 : b5 s; ^5 u0 o6 W
9 b, }' o; e) d/ I3 UDATE: HOTFIX VERSION: 012
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914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD& S- t! @3 O+ x
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files: E% C' y5 t; a' T/ i8 l" ?
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display# G% ~) i/ f' a0 v. y0 e$ M
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
7 Z# Q& Q& C8 C+ x4 u a8 k2 W2 n1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line* T x' z! ^2 _
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.3 U, q0 Z1 k9 [5 n; r
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
+ ^4 c- t2 N5 n9 \3 F* \1 I1151458 GRE CORE GRE crashes on Plan Spatial# Y& r7 ~& z/ b: R
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy; W# J# D* e2 h6 {8 Q
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
7 u Q; P5 [ V1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
# \) `% C, `2 o2 r, R1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
. \. R7 g8 } i9 k/ Y- `" G1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
& C$ n$ ]0 i1 z. R9 h1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places) J) q3 z3 a7 n! q8 @4 i& L' L5 Z
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
! O6 ~. l( N+ X4 g& z8 e; T1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.7 c; b# G8 N+ `
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer" c2 u8 p" O9 k5 _3 j2 u* Q) A
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http://pan.baidu.com/share/link? ... 0&uk=3826038294! M7 p, K+ U( Z
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