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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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DATE: HOTFIX VERSION: 012
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' l3 K5 ^" N) O- E# d( Q% x914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD! G3 ]6 I: ^& ~0 A/ x g" u$ a
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
5 T N& t2 w2 M# J0 m1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display/ I' R/ r! E! I
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.. n5 Q4 G+ J. [- J# N
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line( v8 {- ]4 V. a$ f# K$ w) j' M
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
! {! [# s1 V9 l& _0 r1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
+ ]0 H# R }% t6 Z# h j1151458 GRE CORE GRE crashes on Plan Spatial" W" Y+ r* S. X5 I. e4 i, i
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy( y4 P. S% v2 l! U9 |7 h
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
0 P& A$ r9 x" ?/ Y/ P1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design. V% \& H, U$ D g1 P/ _( `9 L
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger/ V1 h. r, z f1 E! G9 u# N
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
' [- w' \. f% g+ I1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places2 p/ b/ v4 ?+ c. e0 z- V
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail* o: Z4 |$ ^4 J
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
5 B- E; F7 H# R' Q1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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7 l! h ?2 |7 W5 s5 \( \/ s% M* ohttp://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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