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本帖最后由 dsws 于 2013-7-1 20:32 编辑
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5 [$ `' _( W$ hDATE: HOTFIX VERSION: 012
3 I( _1 q' }4 d! i1 v4 Y===================================================================================================================================
8 Y. Q: J8 D; e6 N' eCCRID PRODUCT PRODUCTLEVEL2 TITLE1 ^4 Q! z) Q" u: n- S, o
===================================================================================================================================6 u, Y, b- e. D) M
914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD
3 i9 L3 p. v. }. j7 O1 ~" ?1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files
8 ]& }& Q4 } y: n$ Z2 x1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
4 ], K% N4 N1 X/ _/ b! D9 V1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.
/ A1 G( U# G: C: Y0 k1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line
+ M- Q, R) N/ H+ u" o# W1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.( W7 ~2 b# o# u1 p' [9 _7 F" }
1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.$ y2 K! h1 U0 v
1151458 GRE CORE GRE crashes on Plan Spatial
/ y8 w" j6 v1 h- I7 C: s1 c; d1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy) f) {5 G0 k" h9 T" v# j& S
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]
- G) H4 z% u" t! j1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design6 x$ L w& a: q1 @9 N9 O- K4 O
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger
- N" A9 _9 m& ?$ [' }1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.7 g1 Y7 @3 S! J7 w( D- e
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places+ F/ {0 O+ o7 C0 s( J& s! H
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
3 @8 u; J9 p( g* Y/ W4 ^ z% L1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.2 @* p6 S4 b( \( r
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer
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2 r* P: m7 m* q! V h+ r) h1 Shttp://pan.baidu.com/share/link? ... 0&uk=3826038294
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发表于 2013-7-1 12:00
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