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DATE: 05-24-2013 HOTFIX VERSION: 010
/ v6 _2 Z$ r1 v" n& U8 |4 r===================================================================================================================================
4 B# X; y, H3 n9 U q; D) ^+ vCCRID PRODUCT PRODUCTLEVEL2 TITLE
7 K, s5 k! K( K0 A; X( S; J1 G===================================================================================================================================
! e Q! g8 ^ Y( E! v i1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer1 x, f- V" A! ]/ o% B2 W
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
7 k8 G, p; H0 r. F; [1 }* h1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files) f, T8 t6 F9 \0 \* f+ f
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
v# Q8 r* E$ M; p1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6; Y+ e& ? |2 u z% _! K1 g& {
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
5 ^% V* ]* N8 U2 M1 ~0 P7 J1131775 ADW LRM LRM error with local libs & TDA9 d( \9 z3 C i3 Q# Q! P
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
" y; ^# l# a. z. x3 Z+ z1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo; Z4 h6 D! D# Z1 P+ n
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
' F+ m; G4 W+ i( J- G9 P1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur, e. i1 N4 O! i
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
6 s; j" ] }/ d1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.5 \) d/ o; A) q; ]8 H7 P5 w: H/ y. d9 e
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
u- q4 c2 H1 o1 y1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro; u9 \, [- @" h& [
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.2 V. B. u3 ?' i5 a8 v& R1 _3 L
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
/ h& h [# i- P1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
' a4 P5 e* i$ K$ B0 J$ d4 N }3 Q8 n1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
5 h( g* L+ B* q0 @6 q+ l. f) h1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
; U9 S9 H) P+ `+ V1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor, J- R% j, C0 F! k x; g
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发表于 2013-5-25 09:24
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