|
EDA365欢迎您!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 yulizi 于 2011-12-22 11:18 编辑
' f+ m) e& @7 ]& d3 Z8 ^* Z$ R9 S( Q: ?2 V C
http://kuai.xunlei.com/d/DGOHIFKLICUP' X; H' R) H3 D+ g3 {
2 ~) w2 b; K1 u ?
9 T3 x) n' [" B4 P/ Q
DATE: 12-16-2011 HOTFIX VERSION: 013
/ I4 J) ^% l8 n3 ^) _- X# G===================================================================================================================================
8 W" Y" r/ z. A- L9 pCCRID PRODUCT PRODUCTLEVEL2 TITLE
" v( q7 A4 r# o* \" v( q) p===================================================================================================================================
( X) y3 U* Q- w2 ~3 W4 j& N: U875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.- G/ n7 b: N# i# ^: `5 ~
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
* C5 U2 n( I6 b) N938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
' L7 j% m" F* h# U! ^941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window0 s; e( }8 Z" h8 m
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
; E) H! j" X0 J$ X1 v8 \* b946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat6 K' P4 V+ A6 l6 S; z( |4 w6 ^
946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus.
: l& X- q; U3 `- t950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
) X/ F% R" K: \1 X8 ?3 m& ?953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.5 X; W8 u/ W. w. [+ }: t( k
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block( U; m$ ?; F0 R: n# R* X
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
8 T& C0 \* a e2 M8 k953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?. @* I9 E/ U2 {7 M0 ]$ O( U
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.7 }9 R6 S8 z" g
954498 SCM B2F SCM crashes when importing physical" A/ b9 `6 c9 x$ K# [* g( ?- U& p% R
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?2 Z* e- u. T# K8 i5 r
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3: P- r1 i* V) g
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
8 H/ q' F- J8 z- H4 H, i& U955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.7 a: e: E9 w+ I: [; z9 n: f7 }
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
1 o) X" r, O; A955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S0398 J+ F/ w& U5 @4 D
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME* q. W' l H0 }9 t
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL* o6 e* Y' V- G0 \
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
$ G7 \4 f; W4 Z M955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass6 T/ P6 j' |; v+ {, W( b
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void( \# A6 e: e. a$ z9 b
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.+ |* x$ i1 B% `4 L) O
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file: P2 K# i9 Z2 L) W" @1 u3 U3 z
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.$ g" W- o9 {0 \/ ?1 S, R: {
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
+ a& h2 M; l" S) E) i( G956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
' I5 E) N- R' w$ I956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board! m9 u4 t5 I0 }. S& M; d. h
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component* z6 Q; e: g" h) u
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
. a( F, G$ D& z+ z& q! [956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
, o4 I) ]" h* k( X956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
2 g' _: d# @2 z& Y8 E" I956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
) I/ e% ^# U3 r, K4 G957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist0 S1 E& }+ g) z/ G
957137 APD DXF_IF DXF out command dose not work correctly.6 s5 ?3 S; Z7 V
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
4 _& r% B1 d3 s0 ]7 n$ x957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
2 f; G2 I/ ~# ~$ @957267 CONCEPT_HDL INFRA Packager Error after Import Design
# T: ^5 L7 X' A' v# v957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file9 P4 v9 V! a! d7 Q( q
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.+ R2 k+ K0 x& f4 ?" J8 M
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design1 d/ L. v6 K5 w6 u& M
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
; O" O, E9 Q8 k% F9 s8 N/ f958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
' b7 V5 ~; }. k* R. S- E958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
! S' [. l8 H7 H6 I6 Y! ]959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
1 C7 x* l/ S7 g2 \8 [. F959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs# V$ _' B( n5 J% K% f
959253 CONCEPT_HDL INFRA Design will not open; c0 h6 a9 @# u. r) w2 n& E
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side/ E$ o9 H2 D) [0 Q" M$ c2 t- `6 N( }
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.1 h& z& r5 l/ e% \1 H8 U' P! k( O
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
% s1 M X# ^, f6 Z) c960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
* e0 s% Z( V" D4 K- m; Z7 R960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.+ f: i) J* W3 y0 K; {
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter8 N) t& B3 f: G. \& }9 w* J
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
- {0 P& ]" ~. O961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
) P2 i! C O! z# z, D9 P/ ?( z. l962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
评分
-
查看全部评分
|