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本帖最后由 partime 于 2016-8-10 20:06 编辑 - L) S7 I$ \7 ~8 E- X
. q4 M/ k& a( r# z+ ^0 X不知道有没有人上传分享,我刚下载上传过来,现分享!
; S" v: Q5 A P5 ~! d- [链接在下面,回复可见。顶起来,让更多的人看到!还有CCR,可以看看都修复了什么内容。
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1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result0 |8 q# P- y1 ]9 J
1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S0669 m/ z! D( D* V; e% H& v: j
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
* K8 Z7 F# C: }7 u0 h1 c' {# t 1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
9 W6 J9 M, Y9 F+ K6 ` 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
- t6 g. H" r4 ]$ S, X2 I% h 1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
0 f+ @- L9 V* i4 u 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
U# Z3 M1 `! w3 n! f- U7 k6 B 1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties* |" n2 ~6 R! b9 w" i$ H
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed4 t( y6 R: j# j. Z
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
7 \" M. y" C& _/ F: \ 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component6 K( D! N! S, [
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior o Z! l. p. ?2 I, J6 [
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design# v, _2 s9 s, g$ o3 K. b$ b# b
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM" ~( z/ X2 l5 M) R
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified0 g: `1 ?/ s; x, }0 O1 `
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
/ J. Y5 i2 ?3 i* Z 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
' z q# k" g* A4 a r% w3 h 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor$ _- X" Z) r5 a6 M
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
6 c, f9 R+ z& W: K L& { 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas9 E1 @( q% p" C6 f$ L1 }
1598629 F2B PACKAGERXL Export Physical crashes
& _" P* g$ }) l$ @& M 1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.' i1 @, V7 M+ l2 b u* r+ W* u+ k
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
6 x1 O$ ]1 Z$ q2 q' C 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group/ w0 g/ s- m2 s; Q
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol# d, F5 C5 N: f
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
3 w6 o7 ?: K6 S& b/ E5 x% N 1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses k6 e; Q( y9 B4 h) [* c6 K
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project1 f1 ?- B7 q+ ~
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command3 }3 w% q9 p7 }/ d
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.. Z! c; U& H# `: V5 A
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
* ~3 [" Z; w! B: ] 1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard& r7 t( I4 H+ [+ o
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