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发表于 2014-11-16 10:34
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- ~$ E( p% I" i2 ?' zDATE: 11-14-2014 HOTFIX VERSION: 039
" X5 Y- r5 E$ Z3 X' A===================================================================================================================================
9 B8 R' Y$ u! S- V$ `, }5 ?9 A: sCCRID PRODUCT PRODUCTLEVEL2 TITLE
# O- N( I- f, \3 ^0 ~ b6 Y3 g===================================================================================================================================3 `% C8 l' C6 w7 n7 X* g3 m
1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""
& D% A9 o7 h, U: W6 ?1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding./ C) j- b% k7 S6 G2 [) p6 K
1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default
; x/ [( u) R) t4 P0 _. Y+ C3 T8 U1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports" B4 H" I0 I2 Z+ i1 `2 q9 {) m1 p
1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.
6 p6 Z* b4 X. F: S" L1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown$ k8 Y3 ?% N5 s, k# u/ F% l
1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager
2 i# a# w% H# a3 }5 }1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.- L! l6 A( q1 n: ~) x; s
1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor, G/ w) M8 O* V$ w' u/ s, c
1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA
7 C |% E* R. h4 [/ E& s. f1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX
1 ?9 b ^ N+ j2 x! n7 h+ R1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor8 N( R5 @/ c' Q) b+ X0 x- P# }
1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed.
: |1 h/ E; Z$ b M) K6 f Z1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error
9 u3 r& R6 n1 B. [$ A4 v1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design. Z- z' x# s/ ]9 h& L; _/ W n2 k2 G
1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated$ m/ N( A `4 S6 E+ L9 ~
1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.
& u( N- N* \- D# R& \1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B m1 W& c7 V8 r
1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number
. p( q' b! f* |, G1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack, p' A* l8 E, O# ?+ R
1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores.
- i4 K7 D' Z! `3 }; d% p. R1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.
3 r0 ?! A. a- _" ?1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
; e- x$ N% e! w* j0 h1 X* T( w1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected. J( ]' u5 i+ N3 u) ~% h1 f
1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.
& I' h$ R: ]& |1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
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发表于 2014-11-16 10:30
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发表于 2014-11-16 23:52
