Cadence SPB OrCAD 16.60.016 Hotfix

suiwinder

Cadence SPB OrCAD 16.60.016 Hotfix | 853 mb
- G6 \: B; M7 B9 r9 n DATE: 09-27-2013   HOTFIX VERSION: 016
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/ g( `  }5 Y2 s5 z& d: R: G  m# B===================================================================================================================================
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5 D& i0 a" |; p( ACCRID   PRODUCT        PRODUCTLEVEL2   TITLE

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3 M3 Q0 N, g" Z8 y% B; o+ _548538  CAPTURE        NETLIST_ALLEGRO  Enhancement:Include mechanical parts in Allegro netlist

1076579 CAPTURE        GENERAL          Display value only if value exists
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# T; X2 q. s! t# a" K  r+ E1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.
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1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

* S% [: g+ I5 i# X% Z" }1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled
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; m7 C9 \7 F9 K$ y/ w0 r+ @1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.

! |6 i- m+ H  i- @6 N6 _2 j# r% l1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape
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, u9 d* M3 {3 @* r( _# |9 `; d1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms
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; c: Y+ U/ ]& H8 U' f- ]0 g6 W1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)
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1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor
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$ ^' e  ]4 \2 v6 g2 ~: \1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.
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1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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* u5 [8 b: w5 {" x$ C- C& c1125611 CONCEPT_HDL    OTHER            display unconnected pin in schematic pdf.

1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.
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1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.

' v% v, E; U3 `- O3 _1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set

1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

/ D0 ]4 e: `! k4 \, h2 o+ v% l1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.
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1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells
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: o% [7 y. w" q1142949 CONCEPT_HDL    SKILL            Usage of "Preferences > License Settings?in FSP

. C. J" o3 J. L+ C/ V! j1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract

1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate

5 n7 w$ D1 S+ h1 C! T$ q1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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9 p, ^: \, H. [' L0 K2 }$ n1145286 CONCEPT_HDL    CORE             Directive required for switching off the console
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, f/ ]4 w. o0 ]  T5 K( `1 z) H1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.

1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net
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1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.
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5 s( Z# K  t8 d" N' K, ?# x1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.

3 y( I0 V7 H" @1 L* v1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg
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1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname

1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export

1 M8 }/ c2 P1 k- ~! |1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.

7 ^) b7 Q4 C1 F7 z& r, j1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form

1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.

1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed
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1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?
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, N% Z- s. m6 Q! t1156858 ALLEGRO_EDITOR PADS_IN          PADS Translator: Missing drill on square PTH padstack
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1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.
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+ G8 U) e( a; ^; P( ~: s+ h; g3 P1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation
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8 i$ x1 r) a( l" S* |7 j1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out

1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle

$ a: k# D) c% t7 `1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

  N+ C& a3 U% `  b! B: d' ?. e* Q1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file

1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.
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1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template

1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation

1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines

5 P; h- y, w$ R6 j/ `' S, y3 {1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS

1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro

9 d; ^% L' {0 B# G; |! E  t2 K; |1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape

1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output
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2 J3 L6 A& W2 v' P1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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1162562 CAPTURE        STABILITY        Capture crash on second attempt of pspice netlist creation in 16.6

, r  z8 r- R1 ^. H8 p! M1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly
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, }/ C- w: ?8 N; U1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE

1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database
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5 E# D9 W* [  |+ V2 m# Z- h4 y( K1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.

1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace
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" P; s4 o6 p# j3 @/ A1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin
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6 q0 n0 ?  D" K( N/ L& T1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
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8 e, |% `" k6 K! ~! t5 \$ }6 w1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list
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: j% z. ]9 a5 _! L1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol

1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.
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0 l4 T. V) }- ]' D/ ]" a5 \: u1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.

+ Y2 F2 D3 B$ w8 r1 {1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs

1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window

! x, H5 O5 ?- W% X1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked

1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias

1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
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- J; x$ D" K- d6 L' @) M  r1166074 GRE            CORE             GRE crashes during planning phases
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1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed

: l: _8 X$ g  v/ e1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move

- E6 f1 N% ~0 e5 t1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move

1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue
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# q5 a. C8 {6 K9 @+ }9 V+ V3 I1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash

- ]% e8 Z5 ?6 v, h4 E; T1167887 F2B            OTHER            Improve message on symbol to schematic generation

1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.
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: T4 n7 ?! v* C* T6 j1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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/ J6 P# f. h8 }+ o; n6 Z: M% p3 V1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
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9 _" C) Q) {4 r, |/ Q8 B: Z1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check
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( @/ J! N8 z: a7 p1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty

1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

% ?, Z, x9 b* |, D1 Y2 B6 |  R7 L1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts
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1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule

1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file

1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.

1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components
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$ ?8 h) [6 e. a+ n2 y& R( X1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing

% D, h5 `2 W  h1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
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1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.
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1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads
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1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm

1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific
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5 Q! M# a- M; J4 l. k! X7 @1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically

! l% K8 h) o$ ]' m1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules

1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..

3 P+ _6 m1 X1 E1 W6 |1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl

: O' G2 N, K) P; G" [/ W! G1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.
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1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height

1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer
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% J! m% S5 ^0 f$ V+ t9 Y6 E8 X1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.

( P; t+ _: c# O' z1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.

/ z7 }9 Y( y  J7 A8 ?) b1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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: l; Y. m( u& Y9 i: [1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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( e( n: |) T  A1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version

1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing

1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin
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6 p' _9 `  t" h9 I0 w* I. T1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
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; m+ |3 U+ i5 ^3 ]* l; E3 v1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box
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3 h5 d0 [+ d9 U% P1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".

$ P# [, o- ]( D/ b* \2 D1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!
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1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up

1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash

. i5 Y1 z9 X+ C; s) }1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA
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1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block
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& U$ Z; w) i& F$ M- `: ]1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs
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7 D! ~, M. Q* U& c1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks
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% N$ I; M9 g1 s  |$ v: f9 L7 n4 ~1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.
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" n7 V$ x8 H# e% Z) W" ^Cadence SPB OrCAD 16.60.016 Hotfix
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Download uploaded
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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466