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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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' U8 p) X* p% t4 WDATE: 05-24-2013 HOTFIX VERSION: 010; v4 ]" _: M1 |1 z1 d
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: E" C- P5 g1 K' y; q8 X* {2 a1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer: A4 f6 ?0 a) s4 C. e: p1 f2 O
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border9 s% h+ G+ a; q# @$ m% F1 a* m: g
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
; j; W1 h7 q* k; I! b* j9 J. W2 `1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
* t: L/ R' Q& T! f, I7 {1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6' S b0 ?* w& \/ O& I
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
, t4 @# v& ^, ]$ f& U& @1131775 ADW LRM LRM error with local libs & TDA
- l& p# [* X( Z8 y9 \1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP40 r6 t0 y- k! q. Q& ?; e) g
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
1 c% J/ t+ [, p; Y6 I1 e! l1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
& W. G% b' T& W, E9 K5 J Q1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur. ~5 C4 { E. q
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?$ |8 L' Q' o( ~5 o9 G, [
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.1 C. D& r, P" L% `4 S
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
4 a* }8 H8 ]/ D! R0 J1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro I; B( R# Z2 W a6 `1 `
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
! u2 c& U7 V9 c6 o* m7 U6 C1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
+ _. e, K. u% f. T5 {* F" n; d1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash) S& ]9 U$ C; c% E5 q# ~9 C
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
3 f$ V: s( \7 I5 a7 p, D1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering* w7 f) I" B6 j. j/ R. k
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor# Z& W* L) s7 R- j" B& b# O. ?
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