|
zxli36 发表于 2012-12-29 09:04
$ X0 l0 p$ f7 _% a能不能把你Package时的信息发上来大家看看。 : v D9 X$ w; {6 Y
Package时的信息如下,总共有二十几个问题,几乎所有器件都有问题,这个问题困扰我很长时间了,麻烦您帮我看看,非常感谢0 j7 S5 i/ q: _- W
1 N+ ^6 b' y# M9 m& y5 I& u
-------------------------------------------------------------------------------------------------------------------------------------------------------1 S% h) @$ z% B P# ?: e8 _
Started C:\MentorGraphics\7.9.3EE\SDD_HOME\wv\win32\bin\packagerui.exe F:\demo_dx\demo_dx.prj /d Board1 /nobrowse /config "C:\MentorGraphics"! U( l9 [" ]# i" \, @* r" o
% W" W; ^+ @1 K. i3 Z( E
Packager Version: 020806.00
) d9 n6 ?& v8 }+ B' Y/ l- Y; e' b3 K K# s* a& C7 b4 x6 D
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"' \6 ?! h! l7 l0 m$ L1 y# j
% s# f5 ?8 ]% |4 [# U; lThe Common Database is at "F:\demo_dx\database".
$ |2 F9 @! `' n0 e( j- m5 c7 F0 L& R8 O; ?8 r
The Root of this design is "Deme_Root_1".) N3 B8 G& U9 e4 j" |+ Q) ?! q8 x
7 o% \2 f% v$ u! T! c' g0 l" \
The Front End Snapshot of this design is "DxD".
! ]; d& K2 x+ r/ y
4 p& _: P& F: NThe PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".& X4 a, P) ?- y
. U7 N5 A& Y2 V
The Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
7 x, c9 O4 R- z) D2 G) j- v- ?- X& T4 D4 N8 l& _3 @
Unable to determine the Disable Repackage status.
1 }; S; z! b; p# P0 p!Repackaging will be allowed!. s: a% `6 j8 U+ c8 n4 r# o
4 m5 r: P$ f8 {- ]; ^( o
The PDBs listed in the project file will be searched to satisfy the parts
! G% l+ ]$ U: g6 ~5 \9 {0 ]5 Wrequirements of the iCDB only for parts not already found in the$ a9 W! M& d; p# X7 C
Target PDB.
# H& x+ a6 Q) q5 }
- w2 i5 y9 c1 A% E/ Y0 jThe AllowAlphaRefDes status indicates that reference
9 x1 Q5 _* l, E; I! I9 |designators containing all alpha characters should be deleted
- n4 [$ c+ K8 x7 h aand the relevant symbols repackaged.
1 |; e2 d9 q4 |& C2 Q( \* w( c, _& n8 i( B+ I
The cross mapping of symbol pin names to Part Number pin
) k$ S/ ~3 Q0 m. w+ k3 jnumbers will be checked for packaged symbols and mapped correctly# v, `) b, M% M8 T
for unpackaged symbols.8 v& V3 L' m1 X" ^: z
$ S! |: }, p" c) E" _7 G- r) q' JProperties that have been checked off in the Property Definition Editor
: N+ K( _# \7 e8 g V& x2 ~found at Library Manager/Common Properties will be checked for value) o. e* d! p/ v0 U) J
differences between the PartsDB and the non-null properties on symbols.
& `( M9 O/ ^5 o5 \, P2 c) ~" vThose properties checked off (other than Part Number); @* i0 c6 i/ h9 N4 W) P( x
will not be transferred from the PartsDB to symbols." x) D: ^( P* M9 ^
The following properties were checked off in the Property Definition Editor:" |. m" }& O- X6 F: C
"EPFIXEDWIDTH"
: H, y5 T! w* _"EPFIXEDLENGTH". B5 i- \% r( ?1 Z+ k2 [5 F+ a
"Term". K) O' U7 W H( i
"SIM_MODEL"# Q1 }: `; p$ D: y6 k T! g$ q0 A
"SIM_MODEL_FILE"7 [' a: }1 [5 U2 b4 [4 w$ B
"Array Component"
. {7 \5 N# S) `- x! }"ICX_PART_MODEL"
3 @- b% D4 G( u"Use Verilog"
. l' e# O. u& ?6 E/ \ f"Order"; w1 B# _; W; o6 r
"Parametric"
1 ^% V5 s0 u1 ~, T6 \% b"Value2"
/ T$ ?" |1 ^/ n7 I @. w"Tech"8 |4 l% p2 b% M! l& o
"IBIS". }2 Q' u3 V# }3 T( u; P. s
"Part Label"
9 o8 c8 f9 h1 j$ k* o$ a"VHDL Model"
4 N! I* m2 }/ {4 z' y"Verilog Model"
" |! Q2 O: G6 }9 z% d- n"Cost", p7 t) R( _9 b8 k5 {7 t6 F E9 j
"Tolerance"4 g/ K6 C/ B# m) }5 d% x+ `
"Part Number"9 {) B& H0 R4 f; R
"Value", j( `7 \/ J# E* T
"Part Name"2 l+ _* ^+ g$ h0 p
9 \# {7 l5 [$ D7 k5 n$ @+ L3 R, p* R3 M3 P
Testing of Packaging is being terminated with 22 errors and 1 warnings.2 U7 O; a$ R4 a4 }8 P
Design has NOT been packaged.! L& E6 u2 b; _0 [- T
/ R8 ]1 L; E+ O. u9 z0 D/ NWriting to Log File: Integration\PartPkg.log- R. g. e6 k/ N2 F0 x4 ?
' p9 O5 j. w1 T. IThere have been 22 errors and 1 warnings.. c! L [$ R8 H n
$ C1 D7 m7 }$ C4 t
///////////////////////////////////////////////////////////
: a8 _) B. s) f3 e3 i. D///////////////////////////////////////////////////////////
* {. ~/ d0 B/ W* r( x1 B6 T///// The Log File will now be copied to this window. /////% S" i* B) ^! z$ K% q+ i; E' ^
///// Therefore the data above will also appear below /////
. T1 C8 C" k/ G; }) w5 j///// with more specific error and warning messages. /////
5 R0 w# Q4 A h( q2 i///////////////////////////////////////////////////////////
: g/ W1 y; ~$ ] H" W/ r/ D///////////////////////////////////////////////////////////
+ B% d# U, l* o( n6 ?6 A8 J8 Z, ~" a0 Q/ n4 ?0 f
1 I3 F& b ]& G
Packager) X" h l8 p- q' u3 E* i) g) A
--------. h7 N6 y9 m6 u
4 e7 { a3 c- d5 c; {- S$ ~( S09:27 AM Saturday, December 29, 2012
9 I3 h) v! I* x" S kJob Name: F:\demo_dx\demo_dx.prj
; ^6 s& R5 B$ P5 }/ n4 X* m' | @2 j) X
* W' _. U6 Y+ e( R) k
Packager Version: 020806.00
8 ^$ l, q' {& ^. n9 V8 S9 g( R+ k9 N
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"
* J4 A/ M9 I( g9 _5 q, r3 H9 ]! x; o' z/ `/ x# D; v/ @, y. t4 u H
The Common Database is at "F:\demo_dx\database".2 Z, b$ b. E e4 V
$ }) B% o: T& @* I' g8 y0 z) k( AThe Root of this design is "Deme_Root_1"." R4 Z6 G2 c6 H$ i/ W
5 u: t8 X, S' e& W- u/ \4 eThe Front End Snapshot of this design is "DxD".
/ @. i( N9 O6 d6 b$ i: ~8 s1 U. D5 \; U; k
The PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
5 i7 \) p$ r* \5 J' \! D6 w6 W ?- }$ G
The Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
& a+ F# I% L& D) q+ M: s% N6 S$ S* T! h3 `- }0 q: }7 q
Unable to determine the Disable Repackage status.# ]* H* m3 t: U# H9 |
!Repackaging will be allowed!$ a' U. k6 u( L9 S1 @. o) Q& `
( b+ s* n9 V7 s' L3 c; E
The PDBs listed in the project file will be searched to satisfy the parts( U: ~8 X9 \# f4 Q7 Z5 |
requirements of the iCDB only for parts not already found in the; Z* u* I- a* @0 ^- z8 C
Target PDB.
% N; m0 p4 o, f" _( V
- L) t' {- a2 e7 j; u( t7 GThe AllowAlphaRefDes status indicates that reference1 T$ Z! v. A S! C! ^' h, {
designators containing all alpha characters should be deleted e: g: ?1 \7 P2 U! Z
and the relevant symbols repackaged.' g4 x6 G: F; x8 U' I$ `
6 s) W6 E# l! |' O3 l$ T; `The cross mapping of symbol pin names to Part Number pin
O& d! F3 X; k7 z* w0 i/ Znumbers will be checked for packaged symbols and mapped correctly5 Z5 M" K( \7 }; L3 P' \& W% _
for unpackaged symbols.
; T$ t! L3 d$ |" ^; \: Z
' p. ~, ]0 d* V7 M# V2 oProperties that have been checked off in the Property Definition Editor0 C+ D+ ~3 j6 r0 k7 Y
found at Library Manager/Common Properties will be checked for value; K, a) z% |/ C: X% O
differences between the PartsDB and the non-null properties on symbols.) f% i6 l& z8 g
Those properties checked off (other than Part Number)
) Q4 q& G( Y4 ]. Swill not be transferred from the PartsDB to symbols. j, p! d7 E7 \6 R, Z& H3 m
The following properties were checked off in the Property Definition Editor:
; G) N9 V6 u( _" T; N/ C2 K6 ^"EPFIXEDWIDTH"
# R( r/ ~% c9 q7 t1 A' Y- t"EPFIXEDLENGTH"0 V8 _8 {9 h, D& _' U% ^4 F- s% U
"Term"
8 u2 _5 X$ z0 |"SIM_MODEL"! Z- p$ I& C% _( }3 e% ?( g+ b
"SIM_MODEL_FILE") A: c: a9 f o5 U0 b a
"Array Component"
1 ]; F$ u3 b+ ^- V5 z1 k/ N"ICX_PART_MODEL"' G) ]5 N3 j- d/ v. q9 h
"Use Verilog", [3 ~3 o) O! m7 X
"Order" d' i* Y9 z& D. F: I
"Parametric"
; G+ S7 [: o5 y- Q+ ^"Value2"
* s3 T& n3 g l"Tech"- Q' j1 ?8 Z0 a/ `( D
"IBIS"8 |$ A4 o% b3 X: z" l) F z* C3 T- M
"Part Label") o+ g& K! f- v' t# }* p3 ]) j; W+ \+ Y1 ~
"VHDL Model"
2 f2 U3 j6 q* w. B1 [4 h( h3 w- X"Verilog Model"
4 l6 B7 h7 Y6 q$ _5 W3 d"Cost": H/ B$ c8 a( Y7 q' |/ w/ q- H
"Tolerance"# I8 u- ?1 D: l6 [5 J
"Part Number"
* ?" P! a5 k4 V"Value"& x0 w7 i' V+ S. c/ z
"Part Name"
8 ^) B; x9 \/ ^# f, f+ m, I0 q" \! j- N" `
# ~9 {+ x W7 V GChecking for errors in the ICDB...
# n1 @: e6 h6 \, P3 S3 Y7 f/ u( `, Z: T& J2 C. P5 { P
No errors found. Proceeding with packaging...
9 U2 t4 X: d/ x. H
- u) O+ N5 `1 v& k0 N F1 o
5 C" w5 w7 T/ n: P2 \8 A: A, @. v7 F6 Q/ _+ y5 ]7 y ^
Common Data Base has been read, n( I- J% R/ r7 ^
) \5 g$ @4 G/ }2 M* C6 b* N* @Target PDB Name: Integration\LocalPartsDB.pdb
/ H3 v D8 O4 E+ q1 H4 p9 Q X* M% B( w# ^
WARNING: There are no PartsDB partitions from which to extract parts.! F: L7 `+ F: M0 H
Proceeding using the data in the local PartsDB "Integration\LocalPartsDB.pdb".* U* O4 @* O$ `. n
1 a( h% o* R& Y1 f# x
Number of Part Numbers: 21+ L% B6 i3 M: T
Part Numb: BNC_1 -> Vend Part: 8 c* O _5 Y, K. n' R
Part Numb: CON_EDG_64 -> Vend Part: 5 W9 M/ k7 u3 y- a/ S3 Q, J: z
Part Numb: C_P0.01pF -> Vend Part:
8 F+ v& q- ~* ]% \! }' ?- V- XPart Numb: C_P3.3uF -> Vend Part:
: S6 k9 n2 _" ]* zPart Numb: C_P47pF -> Vend Part: ' q$ w. C L0 h, D
Part Numb: C_0.1uF -> Vend Part:
% g$ ?$ c4 B8 z* H7 L1 `, vPart Numb: DG419AK -> Vend Part:
4 }3 b" T9 A) n( IPart Numb: EPC1064 -> Vend Part: " ~- l) Q6 E8 K" s( `6 A
Part Numb: EPF8282A -> Vend Part: 3 X3 S. U- ^6 ?2 \ U' f
Part Numb: FCT16245 -> Vend Part:
e* [+ B, t# Q3 `! A7 `6 T* c' XPart Numb: LED -> Vend Part: 2 i: \8 x5 W0 R, n- e" V* V8 z( U- P
Part Numb: L_50uH -> Vend Part: 8 i* @' B! J9 u6 U. X) |2 f4 E8 w" B
Part Numb: R_2K -> Vend Part: 5 Y1 a9 L" W1 Z* R7 [( G( Q* s
Part Numb: R_10K -> Vend Part:
% A6 G! G6 Q+ uPart Numb: R_100 -> Vend Part:
7 Z0 v' h3 w3 R; b5 OPart Numb: R_220 -> Vend Part: $ _7 H% a2 r ]1 e
Part Numb: R_510 -> Vend Part: 9 r m$ d; G4 X( Z* G
Part Numb: TC55B4257 -> Vend Part: 9 d: ?2 o% F0 |; k: q$ `
Part Numb: TLC5602A -> Vend Part: : ^( J+ ^+ C7 {# S e x9 K+ }! G+ N& P
Part Numb: 20L10 -> Vend Part:
# C$ b# ?8 Y. E- Y5 hPart Numb: 74ACT574 -> Vend Part:
: E, w. }/ a7 P9 x3 \4 G
: h- n+ y# d5 [! NNumber of Part Names: 1! |2 ^* |# S6 m0 `- E& ^
Part Name: TLE2037A -> Part Number: " x. S: @& Q: v. ^2 N: P
& I6 K! H0 V: G
Number of Part Labels: 04 Q! t" Z5 n" {" V
( g q3 T7 B" q
! p4 T3 \& q( j& E3 v& ~9 d* \
Checking for value differences between non-null symbol properties and PartsDB properties,
/ K" ~' w: _& a: N& T" r! qbut only for those properties checked off in the Property Definition Editor
! ~6 i/ R: s/ ]0 Q& V+ }* D! z' T5 |- u4 {; i
Checking the validity of the packaging of prepackaged schematic
, h1 m- n2 c5 Asymbols. Only the first error in symbols having the same1 X2 B; Y; B& @5 e- i
Reference Designator will be reported.
6 s- U. y% W- T' N* C. u" |" {( t9 s8 `% i! W5 R# N p& D7 a4 J
ERROR: There is no Part Number: CON_EDG_64 in the Parts
7 U% B" w6 P4 X6 @) eDataBase for symbols with Part Name: CON_EDG_64 and Part Label: (null).
& t; L0 b5 ?# n2 D" v9 x2 ^/ b[Please add the Part Number to the PDB either directly
2 \* A# R3 O; t7 ior by having the project file point to a PDB that contains it.]
2 [5 ~( j$ z- w$ ?% T! G7 @The relevant symbols are:5 l7 v1 |3 j! \2 V6 g" {
9 K' }7 m1 h: W Block Deme_Root_1, Page 1, Symbol $1I41 0 C) P( _( @8 K7 ?% i: w* \4 k( i
* T, B" O4 `% o2 x$ X+ _
ERROR: There is no Part Number: FCT16245 in the Parts# ]6 m) h X( y; S4 e5 y- z; ]5 \
DataBase for symbols with Part Name: FCT16245 and Part Label: FCT16245.% e Q, A9 g; @2 s% H. z0 `; T
[Please add the Part Number to the PDB either directly
5 [& q: C3 @+ W; F G) Ror by having the project file point to a PDB that contains it.]" h m6 ^# x7 x& `( ]; I: e6 f- W
The relevant symbols are:1 i7 |* K6 o$ k
/ v! v- S( `8 i) V0 g Block Deme_Root_1, Page 1, Symbol $1I1277
' h- C; n% l6 \9 s- { Block Deme_Root_1, Page 1, Symbol $1I1424 $ Y0 I9 v; `" u d3 i
Block Deme_Root_1, Page 1, Symbol $1I1395 ' V; v9 R3 S; L
Block Deme_Root_1, Page 1, Symbol $1I1366 8 S( Q: \6 m- [# c8 \
Block Deme_Root_1, Page 1, Symbol $1I1337 : o" @; u2 }% @' _& D* |6 n) P, u% q
Block Deme_Root_1, Page 1, Symbol $1I1308 |
|