cadence spb16.3正式发布了

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CADENCE SPB/OrCAD RELEASE 16.3 README --
+ ~1 D9 d8 x8 b( T% \7 M/ w% u% e) e3 ^Windows Version  
Installation Guide  
0 S* e6 ?! s. |$ H% c  oYou can find the Cadence SPB/OrCAD 16.3 Release Installation Guide for Windows, Version
: i$ n6 b# E( y; ?- P5 ^/ z% g16.3 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD.  
Migration Information  
) c* `) Z3 `) IImportant migration information is contained in the Migration Guide for Allegro® Platform
Products Release 16.3, which is available when you install this software or on Cadence Online
! s2 ~/ h+ M; dSupport (http://support.cadence.com).
) i/ w4 e6 ]1 n' a0 v$ l
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
# i! I: O; f' q& V  u* W( }9 p  Dare listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
System Requirements  
+ e' ?* a) j2 O4 Q  W% p* WInformation about minimum and recommended system requirements can be found in the
& K/ C( J' I0 V& _2 z& P& Z: V) ZDocuments folder of the Disk 1 folder in the Allegro Platform System Requirements document
(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com).  

NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
3 G; r& P$ h$ d; TWhat’s New  
8 n- F6 v8 ^0 w% z: A5 o% K% JProduct release notes are available at:  
/ b8 P  U- F( s0 ][url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi[/url]
2 G! h. G- ~/ O8 Png/spb163/prodList.html
* F1 O0 n& y+ w/ ^* X1 B' @KPNS  
1 P( X8 b6 |% R9 J5 t) G7 aThe Known Problems and Solutions (KPNS) document is located at:  
1 Y+ X+ M0 O& k! q/ D[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi[/url]
* V+ j) j- h# x* ?5 g+ ang/spb163/kpnsList.html
Allegro® /SigXplorer® ABIML Libraries for Default Trace Models
with Surface Roughness Effect
$ z# Q& R5 R. M# ?9 w& c3 sThe Allegro /SigXplorer ABIML Library is a free library that includes ABIML libraries for
3 M" L; x, x) U6 }& \( m1 U) gSigXplorer default trace models with surface roughness effect. It is designed to provide accurate
2 q# F) V; {: g# h5 Ytrace models in Allegro /SigXplorer without time consuming EMS2D solver runs. The libraries
7 u* t1 j4 r) R3 B/ I6 V1 b5 Q/ dcan be found at:
http://www.cadence.com/products/pcb/pages/Downloads.aspx
# R& u( `; C( P+ m) LThis ABIML library is provided free of charge for use with Allegro and SigXplorer. The library
is provided as a zipped archive, with installation instructions included.
Custom Environments
. c* a/ Z- r6 e5 r+ v6 |& BCustomers using custom batch files or scripts to set up their environments must add the following
to their path. There is the potential that some Allegro products may not launch without this
setting.
! b( \8 y: ?# n: J, I8 R%CDSROOT%\OpenAccess\bin\win32\opt Downloading and installing SPB Software
+ Z& @0 ^3 F1 w$ R6 R& n: ^% @! K* f' KCadence software can be downloaded from:
http://downloads.cadence.com

NOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software.
1 {8 P9 m9 o8 }: aCadence Channel Partners are listed at:
/ J5 x8 ]! {- q9 h& P7 Phttp://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
$ w8 X! c3 d9 V( B; h) S1 ^
Download Disks 1 through 3 and then extract the zip files into a temporary directory such as
cdnstemp. This will leave you with a directory structure that looks like:  
& Z" |3 N( C2 g  S/ X, l
Disk1 folder
: {  n0 r- r  Z4 e: f1 f7 ADisk2 folder
Disk3 folder
autorun.inf
setup.exe
) J2 v' j/ H. f' z; ysetup.ini
6 b$ R3 z7 {) W  j! N- x# v
) L( \% i# ]" k' M9 Q& EComplete the installation by running setup.exe from the temporary directory or consult
# e2 L$ Y; Y) othe installation guide for more detailed information.  
% j2 k- j2 g% U' ?, R
; \$ x& x2 b, _! g" g0 v! rWARNING: The installer will automatically add the programs in this release to the Windows
  B4 U" t% K0 ~" C, ]" ?Firewall Exceptions list for Windows XP and Service Pack 2 at the end of the installation
1 z0 D9 C( m+ K& w4 f6 t# }% Nprocess. If you do NOT want the installer to do this, you must run setup.exe from a DOS
# L8 s+ W6 }) |5 b7 X' Ccommand prompt window with the following switch:  

setup.exe -nofirewallexceptions  

When the license manager installation is complete, continue by installing the Cadence
products.  
" r* E3 q* D& ~  V2 }. ~7 V7 }
NOTE: If you are prompted to reboot, reboot the machine and log in with the administrator
' @. w2 z" P2 A$ e; N! C& Qprivileges login id to successfully complete the installation. List of Fixed CCRs  
7 W8 Y) h$ O. \' v; _# t8 U•  Enhancement CCRs
. b8 ]# j$ I! k) y2 S' D1 _0 h6 f9 z" D•  Bug CCRs
* r8 F3 B. ~0 Q* [4 G! z" Y0 TEnhancement CCRs:
+ P, i4 b, S: P+ y) P9 V
CCR ID  Description
$ H/ E0 R' B, P, U. I7419  Customer menu options added to Allegro menus
4 F# ^+ q5 u4 A* ^2 n8230  Use via in area constraint does not work
9 c! z8 n$ `3 w2 A  O10658  Modify default formatting for Label texts and linewidths
& K% J9 Y6 I+ b3 M12216  Cannot set color or line width for wires on net-by net basis
13083  flip/mirror design to back side
5 \  a# e! ?- _: V& n2 R13373  Select length of pin graphics
18072  Add docking option for probe cursor box.
21451  Change Probe print trace color yellow to alternate.
32798  pxllite complex hierarchy netname enhancement
( G3 v- U* z$ l% C3 g5 [& I33896  Option for changing the PSpice probe cursor
. Z6 t" ^' ?8 b; i/ ?8 Y7 ^39600  Option to see time spent on allegro database
! h$ {5 k! S( R+ K" _0 E40754  Linux OS support for PSpice
60427  Add different subclasses for pin_number top and bottom
2 @) ]2 X0 [! U5 a) l7 m77555  Capability to export PSpice probe data points in csv format
107219  Capture.ini switch is needed as a Registry entry like PSpice
: \. N+ {8 R3 R  w# z2 [* h; M) |132769  Footprint viewer in CIS should also show pad spacing info
158838  Need easy way to delete marker
159977  need attribute mapping capability in mbs2lib and mbs2brd
, t9 D$ k# }8 n5 B3 x  }  H! m162382  Enhance quickplace using schematic page from ORCAD
( E4 p" e) `& o  k0 a164790  Improve autorouting quality on diff pair w/match length rule
; x" l6 X9 d6 J& e% ~( ?( z0 K( ]205909  Constraint Manager displays in Allegro no graphic mode
+ F( A  u8 R+ N- [9 w' G1 Z210027  Delete dynamic shape removes net name from copied vias
222127  PADS_IN: Constraints are not imported with the design.
6 x: ~; k& d) Q0 U+ p1 S6 s, B236698  Report Unused parts in multiple parts package should be DRC
! O' ~  ^; v: u8 n240525  Add ability to change cursor color in PSpice Probe window
245193  export dxf height information when blocks are unchecked
% J5 V1 Y' }" J# X  y# k254183  Multithreading for DRC and CM analysis in Allegro
: t+ H1 _$ ?7 m: V( b  F2 Y282027  Problem with Split Part and part graphics
282507  request to import IBIS file directly
283698  place by schematic page number window need enhancement
) D& d3 }" I6 }. C' }288540  Schematic page# display order request for Quick place
5 Y1 u" x6 D& \/ M9 G290283  PSpice - Probe - setting background color from UI
290641  Option to copy paste cursor value
298081  Models from Funtion.olb need more explanation
5 y* [- w/ Z1 x. p323813  Need negation and exclusion function in ADE reports
! a' c2 ]* P7 ?' h341484  Wirebond: Tools to generate wirebond manufacturing outputs
0 o5 Y- v  D1 t5 ?, r% I1 y3 S353212  Variant Name is not coming in Standard BOM
360602  Enhancement to Show element on a via
362934  Enhancement for Allegro to utilize Dual Processors.
& w& q0 q# O& O364850  change the font properties of Label Text
% n  ~& z0 I) _6 _/ x4 N367468  Need a real DML_PATH environment variable
380714  Ability to have Power pin set to Not Connect
382860  Display parts and nets in different colors
384488  Add DEVICE and REFDES filter to Signal Model Browser
391487  Ability to have user defined directory for storing distribution files for MC analysis
420008  The renamed differential pair names are different in CM of ConceptHDL and CM of
Allegro.
420023  It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on
CM. 420648  Need to get RF Elements to retain previously entered values
- _9 Z# ^2 H- q) q$ N2 Z429280  ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
% N/ J$ B0 [& c1 u0 |% Y430549  GUI for ADRC XML Rule files
430558  Store last used ADRC rule check ini and check values in .sip database
452606  Can we have last plot as a default  
454452  Allow neighboring/overlapping die pads on same net to go to same finger during wirebond
add.
. E7 Y4 R6 W8 ^( d456854  full AMS Simulator menu without pspice.ini in registry
464056  Setup option to always prompt to baseline a new part
: |3 f( R/ |+ {: i: i4 [  x' d469378  Enhancement : Hide/Unhide feature for trace
475077  Schematic Generation Setup form is missing the Port symbol selection.  It was there in the
, G2 D  u/ I% j' Q$ O15.7 release.
475714  User Guide should mention that Temp Sweep is not honored in AA Flow?
480843  Requesting ability to View > Zoom Mirror current view.
484632  Request for Bond finger to snap to Guide in Free placement of Bond pads
9 s4 }' a6 V/ u; o4 L; k8 ^! [490948  Provide a sketch line and text property form
500550  CRef's should be preserved with the next run of the schgen in the preserve mode.
505284  Enhance The ConceptHDL can set the color for $XR0 property.
512748  improving arc routing
513967  staggered C-line via arrays
, {: y. k: g  f- m" Z515333  Option to specify spacing between Components in the Generated Schematic
524924  Add PSpice enabled part gnd to standard library folder
525748  Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
526818  Retain Hard Packaging Information option does not work for SECs.
528391  SigXplorer measurement is wrong
! k. z3 K* X& W  H  }" R533844  Allegro password not encrypted in the .brd file.
' k% d% I6 \2 Z( c3 R536681  In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge
% r# Z7 E7 X. j5 ZSpacing
536948  Allow  sorting of power symbols
" Y! ?% r- }9 o4 p539407  In ADRC Minimum Shape Check requesting individual "Layer" option
541145  slide command does not support to keeping the existing arc
541214  about supporting OpenDrain Model in Quad2signoise
542414  A function to force diff pair spacing to primary gap.
4 ~3 a- g- v# h7 z# @  G, t8 q542803  A "Minimum Shape Check Soldermask" entry is needed in ADRC
8 J/ }$ }! I! a0 r3 u7 z. j543470  Provide rectangle and line width thickness for Drill legend in NC drill Param
& B2 W" Z: \% S, k543766  Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks
/ i) O" ^  s# B2 s% T# y545408  Cursors are toggled off when deleting a plot
' e4 f  H4 I5 Z& W* x6 b# t& W546891  Enhancement: message improvement when expand design action in Concept
546985  XOR function to allow to compare layers within different or same designs
  y$ d1 U4 H8 U/ V548920  Add a document of which properties can be synced and which cannot be and the files
required
  t* e( Y  J8 w: C4 [0 n' `553669  Add a 3D viewer to Allegro
' Z4 W7 \- e4 y  x' t# z: R* x555183  Wire Bond Report --- Report field should have save function for reuse
556200  Need listing of DE HDL command names and switches.
$ G$ K0 {- a0 f2 O556883  Grid point for Origin to be highlighted
5 Z9 N0 W2 g! \4 W559638  Enhancement for importing height from PADS in allegro
559724  Request cline via arrays to be applied to diffpair nets
- {9 [% a7 }8 ~% c. D6 U' P6 `560134  Show Element Customized Display
1 f* y& D5 E( f' w563957  Enhance Color Dialog form Class/Subclass section to expand vertically when the form size
  {2 h; W7 y5 e! ~5 f5 Aincreases.
568058  Request to have component information available through the context menus
568273  documentation of variables in Capture.ini
+ t; A2 ~, u" u8 G569615  Enhancement to import constraints from Mentor Board Station to Allegro PCB
8 c) e2 `7 K( a* j569680  BOMHDL defaults to the wrong file type when html report type is selected
3 `8 v( w3 Z3 [: A3 N( n- r569784  Request ability to assign netname to via during copy
569863  User would like to set a larger default trace width
570128  Enhancement : Packager setup for subdesign drop down
570195  SiP - Provide option to create/combine BF labeling with additional text required for Bond
! C! e. E, p! l  U9 _( M! n  k( xdiagrams 570861  Unconnected mark does not be removed even after wire is connected to the pin.
8 {' W- [$ W8 [: d1 p575211  Web links in CIS explorer are not working when Firefox 3 as a default Browser
, R8 w0 r1 V! l5 Y9 t9 a577944  Enhancement request to have the drill legend for thru holes and slots to be separated without
being on top of each other
583630  Can Multiple Section pop up box be disabled?
4 y# x" l9 _* f) B6 O0 h& Y" d583712  Ability to have string values for SCHEMATIC_GROUP property
7 {" n1 l5 k% c& x$ q585904  Find a schematic page with help of nets
5 U+ U: I' b2 e' n4 b: s* ^% d- P589316  Document change in Gaussian distribution for PSpice MC from 3 sigma to 1 sigma
$ d; \6 e5 K: X+ N3 K) }589512  RF component snap is 'too clever'
. K* x  B& G  o590246  CIS to Allegro flow to include or ignore constraints same as HDL to Allegro
' K$ ]; k7 b. D$ p; u8 l- |+ Q591306  Suppress RF edit window when changing RF Element properties
0 ~2 n5 H# J+ D% F" m# ~1 v1 c591318  Use RF setup values or retain changed values in RF Element forms
591443  Temporary highlighting is lost when using the Copy command
591450  Provide a dynamic tapering option to RF PCB Route
591489  Would like to suppress RF Snap windowing around the user pick automatically
& k9 Z: @8 ~: P2 r% j591812  Provide move options for the RF Snap command
1 o4 \6 A/ ]( i, V6 U" J591817  Provide easy group and element ID in repackage form
591825  Quickplace for RF Elements
! A; Q6 b- `+ Z( I2 p' h, Q: j+ r591865  Request for more information on 'Other' Netlist formats
) x, o8 V) m" K/ T" G8 b' }) C6 x596392  Publish PDF needs improved error messages for missing installation.
9 [! |! d1 M4 l$ s596555  Request alias symbols documentation to include and clarify when necessary to rotate 180
degrees
596843  Cannot do global search after importing read-only schematic block
; b$ ]* O+ D  ~' e- p3 ?597808  Option to increase the default thickness of all traces in Probe
599499  Plotting from within Allegro does not find path to stipple file
604125  Manufacture>Create Bond finger Soldermask.
605023  Need rats by layer function for Free Viewer
9 N2 b/ W: Z3 C2 u( p. k605112  Dies should not be counted as conductor layers in Design Summary Report of SiP
% o# U6 U7 ^* \2 D' Y3 W/ _* ~605373  importing and Exporting BondWires
& n1 B+ R) v; t! X5 p" g. W5 [* s609035  Voltage_bus part - Make pin number invisible
609561  Enhance Circuit Replicate to support coppers shapes connect lines and vias
610934  Retain user input values in RF PCB forms
612008  Mirror Rules need to be documented for axlTransformObject.
/ j( @) g8 @) C613639  Update Documentation for "split_inst_name" property.
" {: j) @3 w& Y1 n614345  Email facility for Design partition on Solaris does not work
615139  option DMFACTOR  documentation missing in pspcref.pdf
615374  Retain Soldermask Thickness value in 3D Viewer Options
615850  Auto Setup should honor device setup parameters if component value is null
7 g% j$ E, }0 |  W2 F. |6 \2 f615988  PDV WHen importing from Mentor does the browser not remember the last location of
import
; ~1 |3 C: L2 J) T" b616529  15.7 Design Entry HDL fails with Out of Memory message
. ~& ^( K, n1 d, T: h# l9 d( L# T616873  Uppercase characters in design name error should be improved
617976  Enhancement for a way to sort user subclass in define subclass form
( z6 @  [2 L' R, q0 q- s620289  Server 2003 support information in pcbsystemreqs.pdf
620303  Enhancement: Shortcut key for "Select Entire Net"
$ d' |% Z8 m0 D5 A621054  Renamed net in netlist isolates components from the rest of the net.
621955  Offset Via Generator utility should show a warning message if vias are already present.
622203  Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar
* Y6 ^% q4 ?- F$ z8 Wcommands
623218  display pin names associated with a net in net Properties
623908  Mirror Symbols while dynamically moving enhancement
624817  Display padstack name in data tips when hovering over Pad-stack
5 f  U9 N4 t6 O0 m4 c! `8 ]) y+ [625733  In Netlist Report they are requesting square bracket vs angle bracket
0 x8 _8 I( n) d1 l6 Z/ V626605  Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB
XL and PCB GXL
626673  16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows
rotation and allows move but
4 ~8 W) B% i9 ]" K! v- }& g; y629008  enhancements for find command
8 W$ Y6 [& Z% ^/ }629548  Request an Option in Create Plating Bar where it may be directed to a different Subclass 630949  DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire
profile"
630955  SCM does not see design difference after update of fixed die/BGA in cdnsip
3 q# m4 [4 r2 g630973  SCM should see the net assignment made in CDNSIP for Power and Ground pins
1 i# L  N. w1 B. g  |. k631609  Clarify how to generate a cref.dat file in Cadence Help
631697  Want to degass many shapes in succession with custom parameters
# z' Y. T& ?( F) _! A632754  pspPN and lib_list should reflect location of new models in 16.2
633440  Sensitivity not varying components correctly
; J) D$ Z4 R' X633842  Add note to docs regarding padstack quickview
( Z  C6 `" u% J634350  Enhancement suggestions for pop up info boxes.
634877  Export netlist with properties changes scope from global to local
: H0 h0 J9 m2 a5 X9 R635118  SKILL variable to obtain list of Classes and user defined subclasses in a database
8 i5 T3 D6 f1 R# h2 d, O4 d- R% z635233  Place hierarchical pin tool tip
635543  Any command to get the current line/lock type information?
635579  Enhancement for Structured format in parameter file
636930  Die Export option to create symbol either from schematic or layout
637195  Allow for SKill access to backdrill info on padstacks
: N+ |9 X% D) y+ S, d637768  Enhancement to assign different colors to different net based on a unique property
638455  Enhancement: Add some details regarding nomd.lib
638581  ENH - Press ESC button Spreadsheet window disappear
638622  Add note to CM Spacing Domain Region worksheets regarding shape2element clearance
' `9 `; n" y0 p& K" r. V2 v638910  Enhancement to sort the list of available vias alphabetically in the via list ?
639630  Does the Net_Short property work with Modules?
640262  Request object membership count in the status line and forms of CM.
+ C2 ?( t6 t3 b1 R& m. U" G! H. P640280  Provide resizable windows in CM and other apps
2 `  S- k) O" ~640668  File>Change Editor needs ability to go from GXL to Performance L or Design L.
- q1 o, l$ w, ~642095  Ability to disable the Pop-Up description of elements
0 X3 m7 h& Q8 N642298  ENH: For license checkout detailed message
% V8 q; ^* |$ A* q" `- A! @9 I642422  After Copy parameters from one part to other in partmanager forgets previously highlighted
line
6 w1 `5 t& K' i7 U' Q3 ]# o. z642865  Allow format of hyperlinks in ptf files
: c8 [( H" a7 F) Y: R, j642894  ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help
643381  Add an option to ts2dml to allow user specified port ordering.
1 z4 y; B; T. b3 R2 S( L( J. e* L) e643390  Request for a switch or button that would allow Properties to be maintained during a shape
- Y8 N7 h- c: e! @" Gmerge
643625  Bond Wire export to DXF does not support WYSWYG
0 j9 {. e7 [/ I$ i6 J! N1 [643790  Include Associated Components in the Verilog netlist
644216  Store Filter Row Data and Units Of Measurement in site-specific file.
644248  Need a better solution to identify and handle unstuffed components
6 ^/ l  u2 K  S  }4 O644350  Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
0 ~; Y$ U0 y4 x. ~, ?# b646662  Enhancement to add feature to toggle on/off inter communication tool from within PCB
4 C6 R5 J- o8 U" A; e3 FEditor when using DE CIS.
: J8 v! b$ R; P& n) l646981  about the treatment of NO_GLOSS property in Missing Fillets Report
647480  global setting for adrc settings in sip via techfile
' _8 X* P2 `! K4 D1 X647617  Degassing not suppressing shapes less than size specified
648210  Request for Working Layer (WL) model in all tier Allegro tools..
  c- ?1 J% Y' i+ ]) W648218  must delete keyword "multiwire" from Doc
7 s, D  E8 O, A) @) [$ E648533  The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented
648801  Stream Out issue for SPACER
' r2 y0 z# b1 K4 F" o- O" M648930  If two PPT option set names match a given component which one will be used?
% a& Z7 x: t+ p( X6 K; t649603  about spara import
649607  Management of SiP Technology File and Project Information
649610  Management of Part Table (PTF) Files
; s0 {3 [; ?7 n! g6 b649613  Management of Library Lists
651684  documentation improvement request on cross-probing in Capture to Allegro to Constraint
7 x) p8 c* S" j% UManager
& G$ w! L. _9 a1 w1 ~" j1 S4 B8 H652335  Tooltips clutter Place Part dialog.Option to switch it OF and ON
, y9 M1 @. `2 ?) O' K$ t0 }" T( ^652511  Unplace Component command
, U, ~3 o3 v# h( }652547  Description of ForceDBArg1 should be added  to PSpice Users guide 652554  Enhancement request for Allegro to check the vias used to the allowable vias defined in
% t; g* p* `2 z7 bconstraint manager
6 a+ p6 r1 O3 Q# {! N652939  Is there a way to predefine the values for Sample Start Height and Sample Start Length in
, z  {5 j' U* e1 m2 R9 M' t& z/ S" N6 uWire Profile Editor?
- X& P3 M3 O  v9 J+ M$ C0 s0 m653027  Explicit RMB "Done" option is required in Part Developer symbol editor when editing text
653359  Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using
/ n! ]# P  ^" W, othe section command
, G7 h+ q: ^1 f, L653420  Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined
minimum constraint value
653471  Request for Die Text In Wizard option to Flip the DIE coordinates
653825  sigxp_tier was not reset when installing a new product suite
653902  Enhancement: Print Option? setting in Capture.ini file
. U/ m$ I! C5 b, Q8 U5 i( J657180  Enhancement: Tooltip for DRC markers
657187  SI model delete enhancement
) Y/ I; k: X$ r- d' U, w4 ?  J* }657189  SI Model assign enhancement #2
- Z. A  Y' }# m6 ]# R657501  Negative planes doesn't match with Film View
659543  Need a Report to show which Die Pins have no bond wire attached
659661  Function needs for setting the rotation angle in finger by group.
661477  Color192 window sections to be resizable
662215  Please add the function of renaming net by batch command.
662325  Skill code example axlDBGetProperties.txt not correct
! Q7 s" v- D/ Q. l8 g; S662982  When you edit shape, ministat should always enable shape
0 ?, A, Q3 b# B  J, p  b+ f4 l663260  Enhancement: ALG0051 message should be more specific
: E( n3 m$ x( A8 H663754  Enhancement to create Device file when saving dra file on opening another design
0 L2 N8 c+ G( a, I664240  Add CNVPATH in User Preferences to place default CNV files
7 v, u0 p( ~& i/ S2 _8 L665798  163BETA - provide graphical examples to show result of Flexible Shape Editor actions
/ ?! C9 W5 z; y666186  Enhancement FishEye functionality in Variant View Mode
3 N& u. O: t5 y666768  Temporary graphics for modules / groups do not reflect true size
+ N# M9 l- C  F& ~* L. W666775  Update microvia to microvia DRC markings to avoid upper and lower case confusion
667773  Request for ability to set grid definition by entering simple formula
6 Z% N; x' P9 p/ b3 G8 {6 Z668110  Customer wants to enter the value of radius when editing routes.
669373  Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
669380  Add options for ts2dml in MI
  F) q8 E* _7 v8 b669798  Add all 5  Dyn_Thermal_Con_Type property options to Via_Array.
670775  Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
671194  Allegro not to crash when opening unsupported files
4 d; `( L3 N" Z; T: r+ M+ g' _/ z671337  Request performance improvement to access DML libraries from SigXplorer or PCB SI.
671757  Handling of double quotes in HSPICE subckt.
672930  ERROR [DRC0039] Tap may not be connected with the bus Check Entire net
4 r* A5 v, P" }9 n674666  Report the wirebonds XY coordinates
7 }# t/ S# y0 d8 h* P) j675118  Cline change width command enhancement
675151  Insert comment option for database elements
675398  RF PCB setup should automatically point at the project file if Allegro is launched form a
project manager
675551  schematic to sip layout fail
8 d- r7 d5 g- Q676814  Signal Library command with Allegro performance license.
676906  Add switch -regenerate_xnets to the dbdoctor dUI
- v5 h2 [0 ]( [1 ~5 n6 d* R7 g677983  about setting of ibis2signoise option "-d" as default
# \- Z1 M6 F3 @7 [- L8 ~678036  Request for a Physical design compare.
, |7 W" H. ^) X, v) C1 c678798  Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
  J. C5 [# g# {5 ~" r/ K* D679926  Testprep fails with no route keepin. Message in testprep.log ambigious at best
680586  Explanation of functions and macros in online help
682098  Color, font, Text Label in PSpice Probe Window
682695  Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs
rephrased
; W  ?! K- }! t682865  When using PTC format IDF files don't use forward slashes.
684409  Add info for non availability of SIGXP on OrCAD Demo version
, o/ h7 {- O7 f0 V4 A( U: s684713  pin_count view needed for packages
684796  do not delete all vias with DRC for via array 686103  Replace vias evenly spaced apart
686112  Add Connect and Slide keeps cline length
686122  Select objects by polygon
+ Q/ h4 S8 O% C( ?& K% f, o687155  License for batch signoise command
% V- u( ^% ]$ T* \! n1 P: G687187  BGA Full stagger matrix wizard generation
687201  Improvement in Find feature
687685  Documentation of new properties in Variables block
: m- S6 k3 F, ^  A9 e0 l688047  Include blank space in pin name as the illegal character in PDV user guide
, t4 S) t9 }3 e688830  renaming feature discrete library translator
+ L0 M4 p  D' y0 g+ F689720  Need the ability to re-center Vis's in center of Pins when a Die is changed.
0 A! T* X% u4 T: N9 X/ {" {0 W3 {695957  master.tag generated from the table design needs to contain the verilog representation of the
% c/ F$ \9 J# j$ ?7 [3 Q: Ssch.
5 B' L5 I0 Q# h) U  R3 u696661  Add ability in Offset Via Generator to add vias per a given Net
8 ]4 i3 `9 g! H  c696812  provide description for axlCnsPurgeAll() skill function in doc
( V8 L0 q5 D  P8 J697824  Components not installed of variant design should not be extracted into SigXplorer.
698097  Color Dialog form (color192) does not resize correctly
700262  Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the
Allegro PCB SI -L tool)
700712  Defined pin locations are not used when using Die Text-in Wizard with default option
Center pins on symbol origin
701514  axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"
701810  Document what all database sources are supported by Capture CIS
& s% B& U# N. W# t$ b702190  Request support of Windows 2008 Server Editions.
- H+ k% k8 i5 u4 M) {702613  Request SaveRefdesModelAssignments support the include original model path option.
703905  Need Hot Fix number Info on Help >> About
704594  Update symbol removes the text present on Package_Geometry/Silkscreen
704899  Split Bundle Methodology Should Include a Next Function
& ^+ L8 X/ T7 C9 S704904  via matrix should be available in Allegro L and OrCAD PCB Designer
705601  Please make listnindex a public Skill command
; h) f4 s0 h2 y' Q! U$ D+ C705615  During Updating Symbol the text location and size are changed so Reset Text location is
6 `: O3 j$ c0 ]! Y: o! Jconfusing
706165  idf import fails to expand drawing enough to accept text.
# D+ s* X: ^/ O. i2 m706457  Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
706463  Add optional Character in the starting of each line of the file created by axlLogHeader
, X* K8 b0 C- t6 t6 e! A706787  Fillet should remain when user slide the segment far from pin/via.
709119  Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via
Generator
/ j0 O5 _, d$ _2 [0 {" S+ l( k711837  remove the comma from the image of grid value separator
714840  Enhancement: Anti-etch can be recognized as Void element.
" m8 Q+ L& ?4 `715454  Option to configure Design Entry HDL for Cadence Help
1 E. T8 G  ~1 x/ g5 {715713  Enhancement for Wire Short Check during move feature
3 F. ?8 e( l) e1 V6 w716671  About the log file of the na2 interface.
) }. a  i' q2 J' X6 }6 ^717722  Pad designer  File > save as should have recent file name in file field
. q1 H+ z. Y4 h- Y718431  Enhancement request to have DRC checks on negative layers.
- `2 ~' [& ?& ^& Y* t( R719050  Log file should contain username date and time while creating or saving .DRA file
719514  Request length column be added to the Dangling Line Report
6 i6 `/ {  f( Z4 G7 C% y  S720297  about "rip up thermal-relief clines"
722346  DRC checks for mismatches in labeling Net
' j: R8 g- Y/ P- ~7 i# Q723661  Add *.pad in the File of type drop down menu when executing QVUpdate
$ ^- S: d9 G/ A' [724832  Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 -
nil)
! w  i3 m9 w, ^$ p726057  Request incremental DRC update when enabling DFA constraints.
728908  Add Color View Save and Load in Symbol Editor
729947  User would like a metal usage report

" ], P$ d2 I. I( Z! x
9 R6 i% F0 a7 z* K
Bug CCRs:
& J0 K3 l2 ]* q* ?$ G
CCR ID  Description
10116  Add Intersheet references does not work in Complex Hierarchy
11833  Junction not automatically placed when it should be.
1 l+ v8 R1 Z: w- E0 C) w/ ?/ ^4 r16310  Simple hierarchy, intersheet refs not refering to H-block
* N- `# k7 {- S19343  Request for intersheet reference to show grid reference zone
; i8 n' n& B7 ?/ i. P+ m# z22424  Intersheet refs wont work on imported off-page connectors
: M9 e6 ]: @# z+ P4 M/ L% y, y( ^34275  Ibis2signoise fails with legal characters in file
85735  Cref annotations of the P_ID+00 Bus were missing
4 H# U( f2 ~/ _3 Q+ U118279  PSpice command line options problem
134692  DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
136260  Problem with netlisting the design in PSpice
1 `2 ~$ Y2 v; X1 n1 E# y8 ?/ |* [199343  Stackup-Aware SigXplorer
207620  Part in MISC2.OLB has incorrect pin out
270347  Changes to AXL SKILL must be Documented.
283839  lm117 dropout voltage is too large
" b; i8 X& @. x" p: E# U. ^296826  Variant view displays library property
( o2 C; ]+ T$ [+ `; Y+ X299384  Part rotation resets the text to default position
- r3 K9 L8 g* h6 n3 D328647  Replace Cache takes time for network libraries
340323  Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
341035  Dynamic shape fails to fill in design that has cline arcs
390692  Via not getting transferred through the Area Constraint from Allegro to Specctra
405611  Environment variable for SIGNAL_INSTALL_DIR is resolved.
$ J4 F5 h: L1 v428261  spaces at end of pin name Could not create new pin inst library correction utility
436908  The color dialog window will loose the vertical scroll bar after being minimized.
( [6 B0 S2 L! R  V. j9 K437369  Menu selection of Export > Libraries fails to issue the dlib command.
3 O4 M8 r  l* K' J462783  Busname is too long
495671  Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE
+ @8 n9 m1 M. F+ i% @% EProps.
) [2 e! H# C8 M; H. _509393  NC drill legend copies null nc_param.txt to current dir.
# _& Y/ i6 K# o% x: I/ r% T% m512809  Window Prt.part.ptf shrinks by 30% and I have to maximize it.
520802  Global Navigate Zoom to Object needs to remember last setting
/ [: }0 C/ p6 Q" ^528686  During text edit the cursor overlaps a letter rather than in between
531555  The diode BAV99 from library works inverted in compare with the graphical
representation.
532603  Specifying TC1 and TC2 properties does not seem to have effect
547339  CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor
: F4 k# J3 p/ q( i* D548143  Dynamic shape on Etch TOP will not void properly.
3 ]$ A; S8 O1 m. D' S: f/ W- ~550657  Importing registries do not setup printers from MWcontrol
552227  about die export padstack  layer mapping
( a- F4 \4 t0 W( `+ r& ?5 ?- y9 P553035  Cref Synonym and Netsbypage reports do not match netlist
( N& _/ B' }: O% n7 |557660  Incorrect value for I_sinusoidal of pspice_elem
558164  All variants are affected by function regardless of being called for
. r1 u  S9 s) d- E4 o558692  Memory leak problem in loading marker files
565681  Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it
& i; _; W& x( Dshould.
567606  PDV selecting pins in symbol editor shows pins off grid during move
. P: D, \7 D2 S" Z8 U; u' G" e568049  Genview crashes
575353  Large box displayed with place manual-h and no RefDes variable set
% W9 }5 d2 T  `# e  J& |% }8 e581848  not able to edit Padstack Boundary
/ l* i4 }9 {0 p7 h3 E( M591847  Add Intersheet References does not work on simple H design.
1 M& R9 E) N# s% G" g4 u, i592381  Physical Min/Max line width values not check on internal rows or forms.
' ?0 A( k8 B: C2 K0 D593076  Cannot redisplay an invisible OFFPAGE connector's name
598038  Detail button of Markers window with 16.01
600967  wrong order of nodes in PSpiceTemplate for part AD8138/AD
601415  Allegro Design Entry Tutorial corrections.
601531  When using the place manual command and rotating part a ghost image is left behind 603181  Formula to calculate the Actual Temperature for Smoke is incorrect.
/ Q) P5 z0 @. j0 u: }$ |604965  need to document how tcl cmd addComponent handles property values with spaces
1 R- r* B5 O+ N" K7 B7 R605843  Aliased nets do not fully dehighlight when next net is highlighted
% y6 }; ^% e. b5 I606493  Targeted nets are not remaining targets
608150  TestPrep generation is creating DRC errors
608787  Missing Constraints Report
! s5 Y  v5 z6 l3 W. z608942  PDF Publisher output misaligns text in tables
  i0 Y( A/ r3 ]- M( @. l" O3 o* s612511  Error in Flow Tutorial regarding checking default user units
/ R& J+ \' d4 k( e612982  VLIM model giving error that line is too long
: H1 b3 X. b7 K% f- p: `/ \613194  Adding wire bonds with current selection does not yield DRC's, mismatching Allow
DRC violations option.
! B) ?2 d' C4 r" ?613738  Variant BOM report lists identical parts in separate lines due to POWER_GROUP
1 _6 C% t, }: n: E617146  Symbol fails to place through Component Browser
; f7 p8 C8 t- P617327  Change root operation results in SCM crash
" {8 Y0 d7 ~* I' f1 B617784  Trying to open page 2 of the design Capture crashes
/ P( p. m+ S3 ~618150  Property Editor Functionality
3 Q( q. R/ B! f- Q( \9 [618617  Enabling strokes requires checking/unchecking options boxes
618771  PDV error SPLBPD-382 when importing from APD.
619053  Diff Pair problem with creating them in DEHDL.
7 z* z. j( M& V! H" M& p& {+ [619849  Hierarchical Blocks Loosing reference
3 ^2 ]3 A0 c1 {7 N$ I. e620001  Measurement's Maximum range calculation is not correct
620343  Bogus error during schematic write
620826  Changing the units of dimensions does not work
621072  Capture CIS Crash while configuring Database
621163  Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire
7 [' B/ v' R1 g# J1 Y# Nto bondfinger optical short
622263  Drill Customization sort order for oval oblong slots should account for Size Y
622583  Allegro produces erroneous error msg - symbol not found when the placebound is too
large for the board.
622692  Why is VGSR negative for N-channel MOSFETs
6 ^' [6 b  t1 c9 g" |624378  Device file content conflict
624492  Model Editor finds the wrong model definition for BAV99
5 T% b2 G( p: a625462  Symbol pins Property are lost when once stretched
  o9 D- C& ]0 B+ b1 {625519  hspice_mt is not used in Channel Analysis simulation
626674  Allegro CDS_SITE setting don't appear to match documentation
1 a/ n6 w9 G# j. @  a8 u1 I5 K8 \627018  Find Net in instance mode displays twice
627864  EDIF c2esch crashes
628077  Degas not voiding correctly
628265  no "Unused Blind/Buried Via"Report in APD products
1 B  p4 q9 p, R' h) c& I628845  Markers> Packager menu is unselectable even after pxl.mkr is created.
631344  Mouse Wheel Scroll misses the "along with the Control Button"
4 n, U8 _, D9 b! A" c631792  Design Compare not working for OrCAD PCB Designer.
631910  Capture hangs when working with search option
4 U( Q, t- ~+ r1 r633084  controlfile for OrCAD installation does not work with PO100E and PO200E
, M. y# p: w1 w( X+ }$ N3 g* D633086  Generate Part for Pspice Model is incorrect
; C) R# S: Y, B' l$ E- v  v633130  The Verilog netlis is wrong
633223  Running skill from a HDL script causes segmentation fault.
, w' b: q, K) r$ O# R# I- Z& a633473  INPUT_SCRIPT inconsistency when removed from .cpm file
  R5 Z0 ~. o& |  p634075  draw_etch_outline doesn't work for circular shape/arcs
$ N  e( h) i; e+ a6 t" ^635779  Allegro OpenGL distorting text at certain zoom levels
636156  Unable to convert SDT Schematic to Capture Design
/ ~7 a+ N2 `( g636215  Allegro documentation for Export Parameters is incorrect
# D, G, H. ]- |1 ~" [% c636585  Rotating components in Capture reset property position
636688  Signal Model Assignment UI and Find filter association is broken
+ j% n, l0 r8 L  B3 X  U1 s636819  Documentation wrongly indicates that DFA Analysis in unavailable in XL
& R$ S" a; P- e# I' H9 G4 ^9 Y" M637379  No column for ROOM shown in Constraint Manager
$ I/ C: l5 S. I7 w6 Z638140  Intersheet References not offsetting relative to Port
638670  Testprep parameters - padstack selections - Bottom Side replacement text not entirely
6 O3 y% f, {# }8 Y- B' v8 q2 a9 T, y$ |visible. 638987  Change command hangs on customer?s database
639052  Database Objects Preventing Layer From Being Deleted report fails to run
639685  Capture crash while deleting a Hierarchical Port from the Design
639698  HOME variable defined with %USERNAME% doesn't use value of variable.
639829  After setting Zoom key(F10) to a new alias Tool Tip is missing the key number
640127  Correct IDF documentation regarding UNOWNED objects
3 D) I1 e! J' e5 y; Z* Z# B640293  performance issues with scm and large pin count devices
% m) ?# y7 w2 g" V640314  The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
641503  Stop running the VAN check on a PLUMBING body symbol in PDV
; t- p: J; e3 H' x. a641676  Incorrect link to assign refdes help
5 i7 w- a- ]: x* g% S; m: H642053  Drag Connected Objects icon is always display as on
+ D8 t  C" O) d% w& u9 x9 z% R642299  Switch the windows mode by set command
642436  Save As symbol in part editor is not working fine
1 a' y0 K! |, g: ?9 D642713  Materials are not refreshed when material name have only numbers.
4 d( T( M+ Q) p- V, {$ r7 z- o642873  Dynamic shapes out of date message refers to Setup Drawing Options
643721  Attributes with Null values in symbol.css files are removed when saved in PDV
643949  Can not create Region-Class-Class for same net class.
9 [% p# w; V  d( f1 ^644016  APD crashes when creating a tile from LEF file
0 i6 Q& ~( l) ?! D$ U644733  Import reference text file gives incorrect results
644879  Change forms to enforce naming of lib.defs file
% g3 w$ X  L4 y' U6 N: k645046  SG1525A PWM model is reporting unmodel pins and producing incorrect results
# V; b: O, F; \% g: N5 K# Q645427  The save button is not enabled on changing the line width
' X! N( Q6 p8 ^! O+ H645996  con2con fails to parse ppt file correctly
3 C# `  `( t* a6 k0 U5 I646175  Please modify the limit length of "Allegro PCB Editor Limits" correctly.
3 r: d0 z) U8 [+ ^2 @/ G647555  Drill Customization text Non-standard Drill is not readable.
0 T& I1 E% }* X+ c& x# K# N647628  Annotate Type should be removed from PPT Option set files and documentation
' a+ z% Q& T, h7 c+ {648443  Launching SCM without a license is not reported in debug.log
7 v5 ]3 C1 p! C" G9 Y649166  Capture CIS crashes doing Place Database Part with non-admin User rights
* s" b# A8 w( x( E; N& ]649222  Silent install adds extra License Server to CDS_LIC_FILE on the client
0 s9 J" N: x7 _; ?( r649570  PSpice COM Wrapper error while opening Capture PSpice project.
650558  Die Pad layer changed after refresh padstack
650997  Incorrect Pin Shape in CIS Explorer Footprint window
& J; O" \8 H2 t1 B" B7 U651000  "Wire length over parent die" violation is incorrect.
651153  Results for imported CSV inconsistent in PDV
651521  Resizing the display color visibility dialog box corrupts the display
651526  Parts are missing in a advance analysis library list document and font size issue
0 P8 |2 g& D! T7 i651532  Scroll bars disappear after minimizing the color visibility form
652050  Append waveform does not work in 16.2 for .dat files created in previous release with
: a: W. o! x$ n' Kimport text format
652904  significantly low performance issues when using edit interface to delete ports of block
653067  Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?
653784  Off-page connector name change to internal starting like "I12345555"
654580  Save As should update lib.defs without executing the edit die operation
4 ]0 T* {: ~) O) {8 C# f656282  BGA Generator adds outline and RefDes to wrong subclass
656723  visibility of clines in 3d viewer needs ALL instead of just CON field in layers
) [! }& W2 e* Y, X$ N$ y% A657836  Text crop on User Preferences Editor form
: X" S; F& [* R- Z, i$ v. w658347  Rule Continuous Soldermask Coverage Check should not work on Cline Segments
4 h( _# V! y5 n: x+ f! [5 F659437  Move group fails to display anything with Open GL enabled.
2 S0 n+ s$ i5 n5 V: D% A/ g, e3 y660937  Import techfile fails with etch on layer yet layer has no etch
661369  Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
661754  Hyperlink publish pdf to correct page but wrong grid location
9 V  Z5 g1 B$ P7 e0 ]662622  Export Physical reports error Output Layout Filename contains space
* v% J9 ]6 p6 \4 M/ n$ V- E662918  Skill code example for axlReportRegister does not work
% ?/ f4 `3 h1 ^+ s662971  Moving Bondwires disconnect bondfingers.
& R  E9 s% ]3 O663088  Cannot add connect to a C-line in Etch Edit Mode
7 }3 n, v- f+ X9 Y. v) l5 q663220  IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in
7 R2 N/ B. R4 D4 Q. L' |6 R; JDEHDL
663726  ?Each? menu under RefDes is missing in BOM HDL user guide
4 E: \1 U. ^% y- r! v664764  Material changes when layer type is changed 664900  Project manager User Preferences Editor form has text crop.
' i" g4 `6 n$ X1 F! J$ @4 B665236  Unable to import a Quartus-II version 9.0 pin file.
665389  Spread between voids not working for customer design
) [5 ^. f7 J3 i665413  In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
665451  Import - Part logic - information popup window has incorrect user preferences Editor
Category
665661  Wirebond Die Escape Generator failed to generate Clines
3 ~/ G' X# s  j- }: s4 ~& Y666099  Mandating at least one symbol with sizable pins for using size..1(not for size-1..0)
" [8 t0 \- F: s' ?SPLBPD-310/SPLBPD-309 on reload
666667  Relational Table View Browsing Issue
667286  import IFF No Component Shape Line Via found in IFF file.
667751  db(v(out)) and vdb(out) gives different results for FFT
1 y5 Q- X$ \: T( l( Z0 p668080  Improve handling of curved routes
4 K* W! h- S6 b4 I: S668081  Capture Crash during Edit options
" Q( K5 G) n; r. P9 _668393  Dielectric constant or loss tangent values do not update when changing conductor
/ s# y. B0 C" k$ ~# g% T668785  Capture not displaying variant values for Uppercase Display props
, ~. M6 x3 G  Q+ z& v  {3 ]: t, |668799  Placing specific part crashes OrCAD Capture
668876  Text on the Add button is crop on the Edit via list form.
668892  Incorrect Parallel Length data in parallelism report
( `% B8 E) P7 S; [3 o# v- L8 N' g669206  Parallelism rule causing significant performance issues during DRC update
669238  Unable to use permanent highlighting for groups in version 16.x
669323  Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated
0 q  v. C4 |  `3 B9 ]+ Z" @669336  Error in documentation of DE HDL Reference Guide
670874  getVersion() function not reporting tool version
671811  Allegro extracta fails with more than 10 output files
4 l$ y0 {* f% i0 m# Q' }% R672420  User defined property added to component instance is a function property in Allegro
672614  translator converts the symbol "\"  in the original Spice model to "[url=]\\\\[/url]"
( ~3 R7 p1 l+ z$ N672615  Translator generates 6 external nodes should only have up to 5 nodes
672618  Translator generates statement in the dml file: Language=hspice causing Spectre run
' F5 g% B9 h* L/ ^! `! i7 e" k  {! t6 oerrors
672715  Steam_out takes a long time and then fails but the .log file reports a successful export
673279  Same characters are listed as both valid and invalid in naming rules.
673410  search by net name is finding electrical
0 K* b1 T3 ^/ y  i( J674058  Incorrect Variant Report
674291  Library Explorer fails to start and I receive a 'Runtime Error!' pop-up
674555  If the DSN filename contains spaces, autobackup will not write any DBK files to
675192  Adding a second BGA caused dsa_api.c to crash
5 p/ n& V% h$ N- I: w  G7 }; C/ J675231  SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess.
8 u5 Z& D) _  z, Y675562  axlWindowFit() documentation needs to be changed.
# a7 T* }) A) ^675783  SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to
become unplaced from alignment option
676201  Cross section impedance not calculating with single license
676601  behavior of launch product from library manager
+ W" Z/ F- ?! Y; `) {0 c- D677582  mirror of die component on sip designs
678013  Error: Symbol not found, though symbol is mapped in psmpath
' ^) C- s/ d, R* a0 W7 g: K9 }678427  repeatedly placed symbols has strange instance name
* S5 J# C% V, \' d. W* w% a) M5 j678538  Why derive database does not transfer the Schematic Part property to CIS
) H' g- k- ~' G678814  Spin a temp group will not rotate the symbol
678851  Difference in lengths in 16.01 and 16.2
678884  dbdoctor fixes corruption and then it's reintroduced
! k8 O; _) j$ F! G5 B# g679224  dbdoctor states it fixes an error but the error returns
' U  @0 ]/ |6 K+ W( k1 d' I/ b: w679960  Capture crashes from diff pair setup menu
$ e  c0 _/ N& b# T4 @. j680565  Capture dsn files are not properly associated during install
681197  Report generator Hangs Up Allegro PCB Editor
682135  Justification of $PN placeholders not working in 16.2 release
4 C/ o0 y& e5 W; J$ P& ]682204  Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
682331  Incorrect reference to the middle mouse button.
) {5 O3 s6 g! f6 X# _+ V: w4 ~0 u683146  export variant path appears wrong in output folder while two DSN are open
" R1 ~5 N# {; I. O% Q* Q' psimultaneously 683182  DRC0037 shows incorrect Alternate Net Alias.
683379  ERROR in Measurement ConversionGain_XRange
" |1 ?) M' F# `' @0 m3 W( A684180  Sizable pins and vector pins cannot reside together in a component.
684661  via array created wrong results
684700  via array can not be placed on both sides of the cline
684912  16.2 documentation is incorrect for axlDeleteFillet
684915  Incorrect mention of creating graphics template in the PDV user guide
685685  When the customer tried to merge shapes, they disappeared and  do not merge.
686338  ERROR #8012 Database Operation Failed with MS SQL database
686560  Changing pin group property after pin swap resets pin numbers
686736  Load property does not propagate to the associated MECH part
0 M7 q: f. T; @687008  ERROR 8020 after removing Place Icon
687074  Part disappears when you open it
687354  Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package
687385  Publish PDF outputs the net name (with underscore) overlaps with wire.
687708  Smoke deration calculations for Capacitor
687715  Getting Warning TJL will not be smoke checked
688606  Inconsistency in synchronization between bias display and icon
/ j' r6 P) U0 g# F689542  Comma in ESpice model name causes simulation failure
690112  Ignored nets are displayed in simulated crosstalk worksheet in CM
691668  Stimulus editor hangs on doing change type
" F/ ~. |/ `- N  \% A' A- g3 v% W691740  crash when setting coincident uvias in CM beta testing 16.3
/ Z0 w5 K5 m0 Q1 b" F1 E694139  Case difference of net and bus while generating FPGA netlist
694716  Waveforms are flat when using IO b-element in HSpice
695109  Incorrect Diff-pair topology extracted by Paksi-E field solver
% n+ T2 H- B5 U( C0 p695431  csv2ptf fails without providing any error message
- x( N7 m7 g$ d5 n. b# i* e5 `2 O696273  Shape disappears when updated in CDNSIP 16.01 and not following the constraints
696534  Pin Visibility check box doesn't work while creating part from spreadsheet editor
698494  Shape not getting filled correctly
  p) {  `! g3 b/ p" r7 _5 g700160  Error: TVCurve must start at time zero .
9 f8 R6 @% H! S700644  Allegro Crashes on doing Zoom In
7 D6 \/ b7 R4 s, l. I* ?700725  Create Fanout with Via structure add structure from Top to Int. for bottom pins
* F4 L/ V( k. W" K" B701128  Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
702557  Incorrect Behavior with FSP 2 FPGA Option License
703324  Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in
704268  remove ARC and TOGGLE rmb options when in add rectangle or add circle command
2 z# b3 G8 B; v. ^/ v704317  Capture crash when deleting schematic folder
704475  Allegro SI change editor to Allegro PCB XL causes menu problems
9 L7 O$ z2 Z' x3 m7 j705902  ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
705903  Cannot remove a matrix view after modifying the connections
706169  IDF in error has spelling mistake
706613  Diff pair is not extracting properly through design link.
5 v1 F  t' q3 C  X706729  Import properties fails with ERROR [IMP0020]
708134  Place > Manually command menus not refreshing the Placement list
. n) W+ d* b( _$ u* ^) E" x0 h708145  Creating a netlist with Rev. 57AQ is not formatting correctly
708634  Shapes getting incorrectly displayed in 16.2
  x, F" h: j- o5 i7 s710279  ERROR 8020# Place component operation failed.
710859  Unable to create Diff Pair from Autosetup
711739  selecting one component/symbol of class IC can move unrelated component due to
' A1 o% W/ ~; l+ ?7 j2 zincorrect group membership.
712299  Internal application error while creating new design
+ S$ k5 J! M2 z# b$ B2 t0 m: @- f+ e712898  Netrev should not read PARENT_PPT_PART property value while importing the logic,
* O) x- Y+ @, [0 w3 U7 u( vdue to which import logic fails
713465  Problems with dynamic shape creation over routed full-arcs diffpairs
713480  Display issue when adding a custom property to the first bit of the bus.
6 h" c, r) ~& |& T2 w714072  Error while linking database part
( D0 S% Y' y; F4 J0 F  _. n714156  Capture crash while archiving project for external referenced design
716097  Specctra is crash during route.
5 Z4 v/ r0 u4 F0 n/ c" `4 d7 V* O3 z9 h/ ~716212  PACK_SHORT property gives package error for visible POWER pins 717484  Dynamic shape creating voids when moving a symbol
- F  o& I- b2 w718151  Geometry not selected when we click tab for selection filter in pad designer
720092  Difference of behavior for slide for segments in options tab & RMB options
) b7 A+ J+ D4 h! B6 ?7 x! M& |: r720191  Delay tune cannot keep the Gap if the diffpair segment is diagonal.
, o8 t% l5 x; R; D0 t/ E+ P5 `720482  Include steps to Enable PSpice Menus in Design Entry HDL
7 g0 n  R% @, n0 U4 F4 U721415  Two buses are connected without a warning when moved on top of each other
721938  Cross-Section open error
722997  Hyperlink function does not work if zone info. includes hyphen
% y% V' Z3 l; X( {* K723146  Pb during compilation using predicate getFileStrings
723159  Typographical Error under "Synchronizing PTF Information" section
723235  client install results in incorrect, redundant, and problematic cds_lic_file variable
0 \, T8 P$ h1 ~& `, p- e. w724414  State Wins Over Design does not reset the subdesign_suffix block values
724969  Allegro crashes when using place replicate function
725852  Impedance has little difference - BEM2D
6 ]; @# o" d1 h  X: J7 Y0 C& ]726731  SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in
bf not following snap
9 c  L3 ^( X1 d0 i9 b& Q726763  crash during logic import in Allegro CM enabled flow
' U0 I* O4 F" `3 ~( t! R: ], K727663  Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly
729496  Build error in 16.3 and 16.4 cdnsip.exe

gleefly

一般人根本上不去,下不了

jobjin

Good

xiaocat85

有时间扔到网盘上给兄弟们

cassy

等破解完善了再下～

elm99

Very Good

yejingang

BUG可真是多呀

cxt668

有那些bug呀

T45524093

等待网友分享

yjgyiysbcc

刚下载了
for linux版本
8 x; X, S, J- p" b9 e8 u0 k& t" P* O正在试用

suiwinder

有没有好的破解？

jima

运行很慢，bug也多，不如用15.7的

wzwang2000

呵呵，我都用16.5了，楼主动作有点慢哦。